Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-μm CMOS integrated circuits

Ming-Dou Ker; Kuo Chun Hsu

doi:10.1109/RELPHY.2004.1315356

Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-μm CMOS integrated circuits

Ming-Dou Ker^*, Kuo Chun Hsu

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

10 Scopus citations

Abstract

A novel native-NMOS-triggered SCR (NANSCR) is proposed for efficient ESD protection design in a 0.13-μm CMOS process. As compared with the traditional LVTSCR, the trigger voltage, turn-on resistance, turn-on speed, and COM ESD level of NANSCR have been greatly improved to protect the ultra-thin gate oxide against ESD stresses. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger in a 0.13-μm CMOS process with VDD of 1.2 V. A new whole-chip ESD protection scheme realized with the NANSCR devices has been also demonstrated with the consideration of pin-to-pin ESD zapping.

Original language	English
Article number	1315356
Pages (from-to)	381-386
Number of pages	6
Journal	IEEE International Reliability Physics Symposium Proceedings
Volume	2004-January
Issue number	January
DOIs	https://doi.org/10.1109/RELPHY.2004.1315356
State	Published - Apr 2004
Event	2004 IEEE International Reliability Physics Symposium Proceedings, 42nd Annual - Phoenix, AZ., United States Duration: 25 Apr 2004 → 29 Apr 2004

Keywords

CDM
ESD
ESD protection circuit
HBM
Latchup
SCR

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10.1109/RELPHY.2004.1315356

Cite this

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title = "Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-μm CMOS integrated circuits",

abstract = "A novel native-NMOS-triggered SCR (NANSCR) is proposed for efficient ESD protection design in a 0.13-μm CMOS process. As compared with the traditional LVTSCR, the trigger voltage, turn-on resistance, turn-on speed, and COM ESD level of NANSCR have been greatly improved to protect the ultra-thin gate oxide against ESD stresses. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger in a 0.13-μm CMOS process with VDD of 1.2 V. A new whole-chip ESD protection scheme realized with the NANSCR devices has been also demonstrated with the consideration of pin-to-pin ESD zapping.",

keywords = "CDM, ESD, ESD protection circuit, HBM, Latchup, SCR",

author = "Ming-Dou Ker and Hsu, {Kuo Chun}",

year = "2004",

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language = "English",

volume = "2004-January",

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journal = "IEEE International Reliability Physics Symposium Proceedings",

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T1 - Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-μm CMOS integrated circuits

AU - Ker, Ming-Dou

AU - Hsu, Kuo Chun

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N2 - A novel native-NMOS-triggered SCR (NANSCR) is proposed for efficient ESD protection design in a 0.13-μm CMOS process. As compared with the traditional LVTSCR, the trigger voltage, turn-on resistance, turn-on speed, and COM ESD level of NANSCR have been greatly improved to protect the ultra-thin gate oxide against ESD stresses. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger in a 0.13-μm CMOS process with VDD of 1.2 V. A new whole-chip ESD protection scheme realized with the NANSCR devices has been also demonstrated with the consideration of pin-to-pin ESD zapping.

AB - A novel native-NMOS-triggered SCR (NANSCR) is proposed for efficient ESD protection design in a 0.13-μm CMOS process. As compared with the traditional LVTSCR, the trigger voltage, turn-on resistance, turn-on speed, and COM ESD level of NANSCR have been greatly improved to protect the ultra-thin gate oxide against ESD stresses. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger in a 0.13-μm CMOS process with VDD of 1.2 V. A new whole-chip ESD protection scheme realized with the NANSCR devices has been also demonstrated with the consideration of pin-to-pin ESD zapping.

KW - CDM

KW - ESD

KW - ESD protection circuit

KW - HBM

KW - Latchup

KW - SCR

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DO - 10.1109/RELPHY.2004.1315356

M3 - Conference article

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SN - 1541-7026

VL - 2004-January

SP - 381

EP - 386

JO - IEEE International Reliability Physics Symposium Proceedings

JF - IEEE International Reliability Physics Symposium Proceedings

IS - January

M1 - 1315356

Y2 - 25 April 2004 through 29 April 2004

ER -

Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-μm CMOS integrated circuits

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Keywords

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