Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO x on specific interfacial layers exhibiting 65% S.S. reduction and improved I ON

C. J. Su; Y. T. Tang; Y. C. Tsou; P. J. Sung; F. J. Hou; C. J. Wang; S. T. Chung; C. Y. Hsieh; Y. S. Yeh; F. K. Hsueh; K. H. Kao; S. S. Chuang; C. T. Wu; T. Y. You; Y. L. Jian; T. H. Chou; Y. L. Shen; B. Y. Chen; G. L. Luo; T. C. Hong; K. P. Huang; M. C. Chen; Y. J. Lee; Tien-Sheng Chao; Tseung-Yuen Tseng; W. F. Wu; G. W. Huang; J. M. Shieh; W. K. Yeh; Y. H. Wang

doi:10.23919/VLSIT.2017.7998159

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO _x on specific interfacial layers exhibiting 65% S.S. reduction and improved I _ON

C. J. Su, Y. T. Tang, Y. C. Tsou, P. J. Sung, F. J. Hou, C. J. Wang, S. T. Chung, C. Y. Hsieh, Y. S. Yeh, F. K. Hsueh, K. H. Kao, S. S. Chuang, C. T. Wu, T. Y. You, Y. L. Jian, T. H. Chou, Y. L. Shen, B. Y. Chen, G. L. Luo, T. C. HongK. P. Huang, M. C. Chen, Y. J. Lee, Tien-Sheng Chao, Tseung-Yuen Tseng, W. F. Wu, G. W. Huang, J. M. Shieh, W. K. Yeh, Y. H. Wang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

35 Scopus citations

Abstract

Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrO_x (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al₂O₃ IL results in paraelectric behavior, HZO on GeO_x IL exhibits significant FE. High I_on/I_off (> 107) and low subthreshold slope (S.S. ∼ 58 mV/dec.) are demonstrated by a Ge nFinFET with a gate length (L_g) of 60 nm and a FE-HZO/GeO_x gate stack.

Original language	English
Title of host publication	2017 Symposium on VLSI Technology, VLSI Technology 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	T152-T153
ISBN (Electronic)	9784863486058
DOIs	https://doi.org/10.23919/VLSIT.2017.7998159
State	Published - 31 Jul 2017
Event	37th Symposium on VLSI Technology, VLSI Technology 2017 - Kyoto, Japan Duration: 5 Jun 2017 → 8 Jun 2017

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Conference

Conference	37th Symposium on VLSI Technology, VLSI Technology 2017
Country/Territory	Japan
City	Kyoto
Period	5/06/17 → 8/06/17

Access to Document

10.23919/VLSIT.2017.7998159

Cite this

Su, C. J., Tang, Y. T., Tsou, Y. C., Sung, P. J., Hou, F. J., Wang, C. J., Chung, S. T., Hsieh, C. Y., Yeh, Y. S., Hsueh, F. K., Kao, K. H., Chuang, S. S., Wu, C. T., You, T. Y., Jian, Y. L., Chou, T. H., Shen, Y. L., Chen, B. Y., Luo, G. L., ... Wang, Y. H. (2017). Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO _x on specific interfacial layers exhibiting 65% S.S. reduction and improved I _ON. In 2017 Symposium on VLSI Technology, VLSI Technology 2017 (pp. T152-T153). Article 7998159 (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIT.2017.7998159

Su, C. J. ; Tang, Y. T. ; Tsou, Y. C. et al. / Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO _x on specific interfacial layers exhibiting 65% S.S. reduction and improved I _ON. 2017 Symposium on VLSI Technology, VLSI Technology 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. T152-T153 (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{3238f51bd49b486aa7f8fd6e795193e0,

title = "Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO x on specific interfacial layers exhibiting 65% S.S. reduction and improved I ON",

abstract = "Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrOx (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al2O3 IL results in paraelectric behavior, HZO on GeOx IL exhibits significant FE. High Ion/Ioff (> 107) and low subthreshold slope (S.S. ∼ 58 mV/dec.) are demonstrated by a Ge nFinFET with a gate length (Lg) of 60 nm and a FE-HZO/GeOx gate stack.",

author = "Su, {C. J.} and Tang, {Y. T.} and Tsou, {Y. C.} and Sung, {P. J.} and Hou, {F. J.} and Wang, {C. J.} and Chung, {S. T.} and Hsieh, {C. Y.} and Yeh, {Y. S.} and Hsueh, {F. K.} and Kao, {K. H.} and Chuang, {S. S.} and Wu, {C. T.} and You, {T. Y.} and Jian, {Y. L.} and Chou, {T. H.} and Shen, {Y. L.} and Chen, {B. Y.} and Luo, {G. L.} and Hong, {T. C.} and Huang, {K. P.} and Chen, {M. C.} and Lee, {Y. J.} and Tien-Sheng Chao and Tseung-Yuen Tseng and Wu, {W. F.} and Huang, {G. W.} and Shieh, {J. M.} and Yeh, {W. K.} and Wang, {Y. H.}",

note = "Publisher Copyright: {\textcopyright} 2017 JSAP.; 37th Symposium on VLSI Technology, VLSI Technology 2017 ; Conference date: 05-06-2017 Through 08-06-2017",

year = "2017",

month = jul,

day = "31",

doi = "10.23919/VLSIT.2017.7998159",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "T152--T153",

booktitle = "2017 Symposium on VLSI Technology, VLSI Technology 2017",

address = "美國",

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Su, CJ, Tang, YT, Tsou, YC, Sung, PJ, Hou, FJ, Wang, CJ, Chung, ST, Hsieh, CY, Yeh, YS, Hsueh, FK, Kao, KH, Chuang, SS, Wu, CT, You, TY, Jian, YL, Chou, TH, Shen, YL, Chen, BY, Luo, GL, Hong, TC, Huang, KP, Chen, MC, Lee, YJ, Chao, T-S, Tseng, T-Y, Wu, WF, Huang, GW, Shieh, JM, Yeh, WK & Wang, YH 2017, Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO _x on specific interfacial layers exhibiting 65% S.S. reduction and improved I _ON. in 2017 Symposium on VLSI Technology, VLSI Technology 2017., 7998159, Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers Inc., pp. T152-T153, 37th Symposium on VLSI Technology, VLSI Technology 2017, Kyoto, Japan, 5/06/17. https://doi.org/10.23919/VLSIT.2017.7998159

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO _x on specific interfacial layers exhibiting 65% S.S. reduction and improved I _ON. / Su, C. J.; Tang, Y. T.; Tsou, Y. C. et al.
2017 Symposium on VLSI Technology, VLSI Technology 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. T152-T153 7998159 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO x on specific interfacial layers exhibiting 65% S.S. reduction and improved I ON

AU - Su, C. J.

AU - Tang, Y. T.

AU - Tsou, Y. C.

AU - Sung, P. J.

AU - Hou, F. J.

AU - Wang, C. J.

AU - Chung, S. T.

AU - Hsieh, C. Y.

AU - Yeh, Y. S.

AU - Hsueh, F. K.

AU - Kao, K. H.

AU - Chuang, S. S.

AU - Wu, C. T.

AU - You, T. Y.

AU - Jian, Y. L.

AU - Chou, T. H.

AU - Shen, Y. L.

AU - Chen, B. Y.

AU - Luo, G. L.

AU - Hong, T. C.

AU - Huang, K. P.

AU - Chen, M. C.

AU - Lee, Y. J.

AU - Chao, Tien-Sheng

AU - Tseng, Tseung-Yuen

AU - Wu, W. F.

AU - Huang, G. W.

AU - Shieh, J. M.

AU - Yeh, W. K.

AU - Wang, Y. H.

PY - 2017/7/31

Y1 - 2017/7/31

N2 - Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrOx (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al2O3 IL results in paraelectric behavior, HZO on GeOx IL exhibits significant FE. High Ion/Ioff (> 107) and low subthreshold slope (S.S. ∼ 58 mV/dec.) are demonstrated by a Ge nFinFET with a gate length (Lg) of 60 nm and a FE-HZO/GeOx gate stack.

AB - Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrOx (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al2O3 IL results in paraelectric behavior, HZO on GeOx IL exhibits significant FE. High Ion/Ioff (> 107) and low subthreshold slope (S.S. ∼ 58 mV/dec.) are demonstrated by a Ge nFinFET with a gate length (Lg) of 60 nm and a FE-HZO/GeOx gate stack.

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U2 - 10.23919/VLSIT.2017.7998159

DO - 10.23919/VLSIT.2017.7998159

M3 - Conference contribution

AN - SCOPUS:85028090020

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - T152-T153

BT - 2017 Symposium on VLSI Technology, VLSI Technology 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 37th Symposium on VLSI Technology, VLSI Technology 2017

Y2 - 5 June 2017 through 8 June 2017

ER -

Su CJ, Tang YT, Tsou YC, Sung PJ, Hou FJ, Wang CJ et al. Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO _x on specific interfacial layers exhibiting 65% S.S. reduction and improved I _ON. In 2017 Symposium on VLSI Technology, VLSI Technology 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. T152-T153. 7998159. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSIT.2017.7998159