Nano CMOS device quantum simulation: Impact of surface roughness on silicon and Germanium ultra-thin-body MOSFETs

Ultra-Ihin body (UTB) SOI MOSFET is promising for sub-50 nm CMOS technologies [1] However, recent experimental finding [2] suggests the need for serious reconsiderations of its long-term scaling capability into the sub-10 nm body thickness (T_BDDY) regime. Two new phenomena attributed to surface roughness (SR) are identified [2]; they are enhanced threshold voltage (V_TH) shifts and drastic. degradation of mobility with a_TBODYdependence [2,3]. In this work, we detail a study of these two phenomena in UTB MOSFETs with sub 10 nm TaODY Si and Ge channels. Firstly, the phenomena of enhanced V_THshifts is modeled by accounting for the fluctuation of quantized energy levels due to SR up to second order approximation. Good corroboration with experimental results [2] is obtained. Our model is then applied to examine the impact of enhanced V_THshifts on metal gate work function requirements. Secondly, we modeled the SR-limited electron and hole mobility and discuss their impact on the choice of suiface orientations. Mobility anisotropy are also examined for the various surface orientations.