Multi-gigabit serial link transmitter- Off-chip and on-chip

Shyh-Jye Jou; Chih Hsien Lin; Chih Ning Chen; You Jiun Wang; Ju Yuan Hsiao

doi:10.1109/EITC.2005.1544368

Multi-gigabit serial link transmitter- Off-chip and on-chip

Shyh-Jye Jou^*, Chih Hsien Lin, Chih Ning Chen, You Jiun Wang, Ju Yuan Hsiao

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Multi-Gbps serial link transmitter for both off-chip and on-chip transmission are presented. For off-chip transmission, a new pre-emphasis design methodology and circuits for a 4/2 PAM transmitter over cable are proposed. A test chip of transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented using tsmc 0.18 um CMOS process. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and simulation results. For on-chip transmission, SerDes based serial link architecture is used in on-chip application. Using tsmc 0.13 um CMOS process, the operation speed and power consumption are 5 Gbps and 3.2 mW respectively with the interconnect area is half of parallel architecture.

Original language	English
Title of host publication	Emerging Information Technology Conference 2005
Pages	137-140
Number of pages	4
DOIs	https://doi.org/10.1109/EITC.2005.1544368
State	Published - 1 Dec 2005
Event	Emerging Information Technology Conference 2005 - Taipei, Taiwan Duration: 15 Aug 2005 → 16 Aug 2005

Publication series

Name	Emerging Information Technology Conference 2005
Volume	2005

Conference

Conference	Emerging Information Technology Conference 2005
Country/Territory	Taiwan
City	Taipei
Period	15/08/05 → 16/08/05

Access to Document

10.1109/EITC.2005.1544368

Cite this

@inproceedings{635c4d9f32314d4ea7f6465153b74802,

title = "Multi-gigabit serial link transmitter- Off-chip and on-chip",

abstract = "Multi-Gbps serial link transmitter for both off-chip and on-chip transmission are presented. For off-chip transmission, a new pre-emphasis design methodology and circuits for a 4/2 PAM transmitter over cable are proposed. A test chip of transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented using tsmc 0.18 um CMOS process. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and simulation results. For on-chip transmission, SerDes based serial link architecture is used in on-chip application. Using tsmc 0.13 um CMOS process, the operation speed and power consumption are 5 Gbps and 3.2 mW respectively with the interconnect area is half of parallel architecture.",

author = "Shyh-Jye Jou and Lin, {Chih Hsien} and Chen, {Chih Ning} and Wang, {You Jiun} and Hsiao, {Ju Yuan}",

year = "2005",

month = dec,

day = "1",

doi = "10.1109/EITC.2005.1544368",

language = "English",

isbn = "0780393295",

series = "Emerging Information Technology Conference 2005",

pages = "137--140",

booktitle = "Emerging Information Technology Conference 2005",

note = "null ; Conference date: 15-08-2005 Through 16-08-2005",

}

TY - GEN

T1 - Multi-gigabit serial link transmitter- Off-chip and on-chip

AU - Jou, Shyh-Jye

AU - Lin, Chih Hsien

AU - Chen, Chih Ning

AU - Wang, You Jiun

AU - Hsiao, Ju Yuan

PY - 2005/12/1

Y1 - 2005/12/1

N2 - Multi-Gbps serial link transmitter for both off-chip and on-chip transmission are presented. For off-chip transmission, a new pre-emphasis design methodology and circuits for a 4/2 PAM transmitter over cable are proposed. A test chip of transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented using tsmc 0.18 um CMOS process. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and simulation results. For on-chip transmission, SerDes based serial link architecture is used in on-chip application. Using tsmc 0.13 um CMOS process, the operation speed and power consumption are 5 Gbps and 3.2 mW respectively with the interconnect area is half of parallel architecture.

AB - Multi-Gbps serial link transmitter for both off-chip and on-chip transmission are presented. For off-chip transmission, a new pre-emphasis design methodology and circuits for a 4/2 PAM transmitter over cable are proposed. A test chip of transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented using tsmc 0.18 um CMOS process. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and simulation results. For on-chip transmission, SerDes based serial link architecture is used in on-chip application. Using tsmc 0.13 um CMOS process, the operation speed and power consumption are 5 Gbps and 3.2 mW respectively with the interconnect area is half of parallel architecture.

UR - http://www.scopus.com/inward/record.url?scp=33751189369&partnerID=8YFLogxK

U2 - 10.1109/EITC.2005.1544368

DO - 10.1109/EITC.2005.1544368

M3 - Conference contribution

AN - SCOPUS:33751189369

SN - 0780393295

SN - 9780780393295

T3 - Emerging Information Technology Conference 2005

SP - 137

EP - 140

BT - Emerging Information Technology Conference 2005

Y2 - 15 August 2005 through 16 August 2005

ER -

Multi-gigabit serial link transmitter- Off-chip and on-chip

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