Shyh-Jye Jou*, C. W. Jen, W. Z. Shen, C. L. Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


MOTA; a new NMOS and CMOS timing simulator, is presented. Basically, it employs a one sweep nonlinear Gauss-Seidal relaxation technique to decouple node equations, and this results in a linear performance on the computation time over the number of the gates of the circuit. It has three features: (a) it provides a 'SUBCIRCUIT' capability to simulate tightly-coupled circuit blocks. This solves the inaccuracy and the instability problems which are usually encountered in existing timing simulators, (b) it employs a physical table model for MOS devices with only 250 storage points, and (c) it utilizes a simple variable time step control scheme and internal and external bypass schemes to increase the simulation speed. Examples show that it is approximately 60 times faster than SPICE2G-5 while giving comparable precision.

Original languageEnglish
Pages (from-to)193-199
Number of pages7
JournalIEE Proceedings I: Solid State and Electron Devices
Issue number5
StatePublished - 1 Jan 1986


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