MOS-bounded diodes for on-chip ESD protection in a 0.15-μm shallow-trench-isolation salicided CMOS process

Ming-Dou Ker; Kun Hsien Lin; Che Hao Chuang

doi:10.1109/VTSA.2003.1252558

MOS-bounded diodes for on-chip ESD protection in a 0.15-μm shallow-trench-isolation salicided CMOS process

Ming-Dou Ker, Kun Hsien Lin, Che Hao Chuang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Novel diode structures without the shallow trench isolation (STI) across the p/n junction for ESD protection in a 0.15-um CMOS process are proposed. A NMOS (PMOS) is especially inserted into the diode structure to form the NMOS-bounded (PMOS-bounded) diode, which is used to block the STI isolation across the p/n junction in the diode structure. Without the STI boundary across the p/n junction of diode structure, the proposed PMOS-bounded and NMOS-bounded diodes can provide more effective protection to the internal circuits, as compared to the other diode structures under reversebiased condition. Such PMOS-bounded and NMOS-bounded dodes are fully process-compatible to general CMOS processes without additional process modification or mask layers.

Original language	English
Title of host publication	VLSI 2003 - 2003 20th International Symposium on VLSI Technology, Systems and Applications, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	84-87
Number of pages	4
ISBN (Electronic)	0780377656
DOIs	https://doi.org/10.1109/VTSA.2003.1252558
State	Published - 1 Jan 2003
Event	20th International Symposium on VLSI Technology, Systems and Applications, VLSI 2003 - Hsinchu, Taiwan Duration: 6 Oct 2003 → 8 Oct 2003

Publication series

Name	International Symposium on VLSI Technology, Systems, and Applications, Proceedings
Volume	2003-January
ISSN (Print)	1930-8868

Conference

Conference	20th International Symposium on VLSI Technology, Systems and Applications, VLSI 2003
Country/Territory	Taiwan
City	Hsinchu
Period	6/10/03 → 8/10/03

Access to Document

10.1109/VTSA.2003.1252558

Cite this

Ker, M.-D., Lin, K. H., & Chuang, C. H. (2003). MOS-bounded diodes for on-chip ESD protection in a 0.15-μm shallow-trench-isolation salicided CMOS process. In VLSI 2003 - 2003 20th International Symposium on VLSI Technology, Systems and Applications, Proceedings (pp. 84-87). Article 1252558 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VTSA.2003.1252558

Ker, Ming-Dou ; Lin, Kun Hsien ; Chuang, Che Hao. / MOS-bounded diodes for on-chip ESD protection in a 0.15-μm shallow-trench-isolation salicided CMOS process. VLSI 2003 - 2003 20th International Symposium on VLSI Technology, Systems and Applications, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 84-87 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

@inproceedings{decf8834f97e4dce9b018217ffa950ea,

title = "MOS-bounded diodes for on-chip ESD protection in a 0.15-μm shallow-trench-isolation salicided CMOS process",

abstract = "Novel diode structures without the shallow trench isolation (STI) across the p/n junction for ESD protection in a 0.15-um CMOS process are proposed. A NMOS (PMOS) is especially inserted into the diode structure to form the NMOS-bounded (PMOS-bounded) diode, which is used to block the STI isolation across the p/n junction in the diode structure. Without the STI boundary across the p/n junction of diode structure, the proposed PMOS-bounded and NMOS-bounded diodes can provide more effective protection to the internal circuits, as compared to the other diode structures under reversebiased condition. Such PMOS-bounded and NMOS-bounded dodes are fully process-compatible to general CMOS processes without additional process modification or mask layers.",

author = "Ming-Dou Ker and Lin, {Kun Hsien} and Chuang, {Che Hao}",

year = "2003",

month = jan,

day = "1",

doi = "10.1109/VTSA.2003.1252558",

language = "English",

series = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "84--87",

booktitle = "VLSI 2003 - 2003 20th International Symposium on VLSI Technology, Systems and Applications, Proceedings",

address = "美國",

note = "20th International Symposium on VLSI Technology, Systems and Applications, VLSI 2003 ; Conference date: 06-10-2003 Through 08-10-2003",

}

Ker, M-D, Lin, KH & Chuang, CH 2003, MOS-bounded diodes for on-chip ESD protection in a 0.15-μm shallow-trench-isolation salicided CMOS process. in VLSI 2003 - 2003 20th International Symposium on VLSI Technology, Systems and Applications, Proceedings., 1252558, International Symposium on VLSI Technology, Systems, and Applications, Proceedings, vol. 2003-January, Institute of Electrical and Electronics Engineers Inc., pp. 84-87, 20th International Symposium on VLSI Technology, Systems and Applications, VLSI 2003, Hsinchu, Taiwan, 6/10/03. https://doi.org/10.1109/VTSA.2003.1252558

MOS-bounded diodes for on-chip ESD protection in a 0.15-μm shallow-trench-isolation salicided CMOS process. / Ker, Ming-Dou; Lin, Kun Hsien; Chuang, Che Hao.
VLSI 2003 - 2003 20th International Symposium on VLSI Technology, Systems and Applications, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2003. p. 84-87 1252558 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings; Vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - MOS-bounded diodes for on-chip ESD protection in a 0.15-μm shallow-trench-isolation salicided CMOS process

AU - Ker, Ming-Dou

AU - Lin, Kun Hsien

AU - Chuang, Che Hao

PY - 2003/1/1

Y1 - 2003/1/1

N2 - Novel diode structures without the shallow trench isolation (STI) across the p/n junction for ESD protection in a 0.15-um CMOS process are proposed. A NMOS (PMOS) is especially inserted into the diode structure to form the NMOS-bounded (PMOS-bounded) diode, which is used to block the STI isolation across the p/n junction in the diode structure. Without the STI boundary across the p/n junction of diode structure, the proposed PMOS-bounded and NMOS-bounded diodes can provide more effective protection to the internal circuits, as compared to the other diode structures under reversebiased condition. Such PMOS-bounded and NMOS-bounded dodes are fully process-compatible to general CMOS processes without additional process modification or mask layers.

AB - Novel diode structures without the shallow trench isolation (STI) across the p/n junction for ESD protection in a 0.15-um CMOS process are proposed. A NMOS (PMOS) is especially inserted into the diode structure to form the NMOS-bounded (PMOS-bounded) diode, which is used to block the STI isolation across the p/n junction in the diode structure. Without the STI boundary across the p/n junction of diode structure, the proposed PMOS-bounded and NMOS-bounded diodes can provide more effective protection to the internal circuits, as compared to the other diode structures under reversebiased condition. Such PMOS-bounded and NMOS-bounded dodes are fully process-compatible to general CMOS processes without additional process modification or mask layers.

UR - http://www.scopus.com/inward/record.url?scp=84863293259&partnerID=8YFLogxK

U2 - 10.1109/VTSA.2003.1252558

DO - 10.1109/VTSA.2003.1252558

M3 - Conference contribution

AN - SCOPUS:84863293259

T3 - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

SP - 84

EP - 87

BT - VLSI 2003 - 2003 20th International Symposium on VLSI Technology, Systems and Applications, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 20th International Symposium on VLSI Technology, Systems and Applications, VLSI 2003

Y2 - 6 October 2003 through 8 October 2003

ER -

Ker MD, Lin KH, Chuang CH. MOS-bounded diodes for on-chip ESD protection in a 0.15-μm shallow-trench-isolation salicided CMOS process. In VLSI 2003 - 2003 20th International Symposium on VLSI Technology, Systems and Applications, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2003. p. 84-87. 1252558. (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). doi: 10.1109/VTSA.2003.1252558

MOS-bounded diodes for on-chip ESD protection in a 0.15-μm shallow-trench-isolation salicided CMOS process

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this