Morphological image processing on VLSI opto-electronic array processors

Wai Chi Fang, Timothy Shaw, Jeffrey Yu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


A full-custom op to-electronic VLSI design for high-speed morphological image processing has been developed by combining a 2- dimensional fine-grain parallel array architecture with on-chip focalplane photodetectors and transmitters. The processor array performs morphological functions on the opto-detected binary image with a programmable structuring element of any size. A specific language called MIPL is defined for morphological image processing and fully supported by the MIP hardware. Sophisticated morphological image processing algorithms were implemented by executing specific parallel programs (written in MIPL) on the MIP. An 8x8 array processor prototype chip has been designed in 1.2 mm × 1.2 mm silicon area using the MOSIS 2-μm CMOS process.

Original languageEnglish
Title of host publicationWorkshop on VLSI Signal Processing 1992
EditorsWojtek Przytula, Kung Yao, Rajeev Jain, Jan Rabaey
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages10
ISBN (Electronic)0780308115, 9780780308114
StatePublished - 1 Jan 1992
Event6th IEEE Workshop on VLSI Signal Processing - Los Angeles, United States
Duration: 28 Oct 199230 Oct 1992

Publication series

NameWorkshop on VLSI Signal Processing 1992


Conference6th IEEE Workshop on VLSI Signal Processing
Country/TerritoryUnited States
CityLos Angeles


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