@inproceedings{b4269a18df5a488890f8604624d1a4b2,
title = "Morphological image processing on VLSI opto-electronic array processors",
abstract = "A full-custom op to-electronic VLSI design for high-speed morphological image processing has been developed by combining a 2- dimensional fine-grain parallel array architecture with on-chip focalplane photodetectors and transmitters. The processor array performs morphological functions on the opto-detected binary image with a programmable structuring element of any size. A specific language called MIPL is defined for morphological image processing and fully supported by the MIP hardware. Sophisticated morphological image processing algorithms were implemented by executing specific parallel programs (written in MIPL) on the MIP. An 8x8 array processor prototype chip has been designed in 1.2 mm × 1.2 mm silicon area using the MOSIS 2-μm CMOS process.",
author = "Fang, {Wai Chi} and Timothy Shaw and Jeffrey Yu",
year = "1992",
month = jan,
day = "1",
doi = "10.1109/VLSISP.1992.641060",
language = "English",
series = "Workshop on VLSI Signal Processing 1992",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "277--286",
editor = "Wojtek Przytula and Kung Yao and Rajeev Jain and Jan Rabaey",
booktitle = "Workshop on VLSI Signal Processing 1992",
address = "United States",
note = "6th IEEE Workshop on VLSI Signal Processing ; Conference date: 28-10-1992 Through 30-10-1992",
}