TY - GEN
T1 - More effective power-gated circuit optimization with multi-bit retention registers
AU - Lin, Shu Hung
AU - Lin, Po-Hung
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2015/1/5
Y1 - 2015/1/5
N2 - Applying retention registers is one of the most effective and efficient approaches to keep flip-flop states in power-gated circuits during the sleep mode. Instead of replacing each flip-flop in a power-gated circuit with a single-bit retention register (SBRR), recent research has shown that applying multi-bit retention registers (MBRRs) can effectively reduce the storage size, and hence save more chip area and leakage power. However, the previous work simply adopted greedy heuristics for power-gated circuit optimization with MBRRs, which first break feedback paths and then iteratively replace a flip-flop covering the maximum number of (k-1)-link paths with a k-bit retention register. Different from the previous work, this paper presents an even more effective approach based on integer-linear-programming (ILP) formulation with simultaneous consideration of all feedback paths. Experimental results show that the proposed approach can further reduce up to 46% storage size compared with the previous work.
AB - Applying retention registers is one of the most effective and efficient approaches to keep flip-flop states in power-gated circuits during the sleep mode. Instead of replacing each flip-flop in a power-gated circuit with a single-bit retention register (SBRR), recent research has shown that applying multi-bit retention registers (MBRRs) can effectively reduce the storage size, and hence save more chip area and leakage power. However, the previous work simply adopted greedy heuristics for power-gated circuit optimization with MBRRs, which first break feedback paths and then iteratively replace a flip-flop covering the maximum number of (k-1)-link paths with a k-bit retention register. Different from the previous work, this paper presents an even more effective approach based on integer-linear-programming (ILP) formulation with simultaneous consideration of all feedback paths. Experimental results show that the proposed approach can further reduce up to 46% storage size compared with the previous work.
UR - http://www.scopus.com/inward/record.url?scp=84936883595&partnerID=8YFLogxK
U2 - 10.1109/ICCAD.2014.7001354
DO - 10.1109/ICCAD.2014.7001354
M3 - Conference contribution
AN - SCOPUS:84936883595
VL - 2015-January
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 213
EP - 217
BT - 2014 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 33rd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014
Y2 - 2 November 2014 through 6 November 2014
ER -