Monolithic microprocessor and RF transceiver in 0.25-micron FDSOI CMOS

E. McShane; K. Shenai; L. Alkalai; E. Kolawa; V. Boyadzhyan; B. Blaes; Wai-Chi  Fang

doi:10.1109/GLSV.1999.757446

Monolithic microprocessor and RF transceiver in 0.25-micron FDSOI CMOS

E. McShane^*, K. Shenai, L. Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, Wai-Chi Fang

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

A monolithic RFIC in 0.25-micron fully-depleted SOI CMOS has been designed consisting of a microcoded 8-bit 33-MHz microprocessor, a 400-MHz 8-bit ASK-modulated RF transceiver, and two integrated dc-dc voltage converters for power management. This architecture exploits a low-power (sub 2-V) digital process for mixed-signal VLSI in a die size measuring 2.2 mm × 2.2 mm.

Original language	English
Title of host publication	Proceedings of the IEEE Great Lakes Symposium on VLSI
Publisher	IEEE
Pages	332-333
Number of pages	2
ISBN (Print)	0769501044
DOIs	https://doi.org/10.1109/GLSV.1999.757446
State	Published - 1999
Event	Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA Duration: 4 Mar 1999 → 6 Mar 1999

Publication series

Name	Proceedings of the IEEE Great Lakes Symposium on VLSI
ISSN (Print)	1066-1395

Conference

Conference	Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)
City	Ann Arbor, MI, USA
Period	4/03/99 → 6/03/99

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10.1109/GLSV.1999.757446

Cite this

@inproceedings{0af89a3fe5f143c9b2c7f2c5aa180f6d,

title = "Monolithic microprocessor and RF transceiver in 0.25-micron FDSOI CMOS",

abstract = "A monolithic RFIC in 0.25-micron fully-depleted SOI CMOS has been designed consisting of a microcoded 8-bit 33-MHz microprocessor, a 400-MHz 8-bit ASK-modulated RF transceiver, and two integrated dc-dc voltage converters for power management. This architecture exploits a low-power (sub 2-V) digital process for mixed-signal VLSI in a die size measuring 2.2 mm × 2.2 mm.",

author = "E. McShane and K. Shenai and L. Alkalai and E. Kolawa and V. Boyadzhyan and B. Blaes and Wai-Chi Fang",

year = "1999",

doi = "10.1109/GLSV.1999.757446",

language = "English",

isbn = "0769501044",

series = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

publisher = "IEEE",

pages = "332--333",

booktitle = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

note = "Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) ; Conference date: 04-03-1999 Through 06-03-1999",

}

McShane, E, Shenai, K, Alkalai, L, Kolawa, E, Boyadzhyan, V, Blaes, B & Fang, W-C 1999, Monolithic microprocessor and RF transceiver in 0.25-micron FDSOI CMOS. in Proceedings of the IEEE Great Lakes Symposium on VLSI. Proceedings of the IEEE Great Lakes Symposium on VLSI, IEEE, pp. 332-333, Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99), Ann Arbor, MI, USA, 4/03/99. https://doi.org/10.1109/GLSV.1999.757446

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AU - McShane, E.

AU - Shenai, K.

AU - Alkalai, L.

AU - Kolawa, E.

AU - Boyadzhyan, V.

AU - Blaes, B.

AU - Fang, Wai-Chi

PY - 1999

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AB - A monolithic RFIC in 0.25-micron fully-depleted SOI CMOS has been designed consisting of a microcoded 8-bit 33-MHz microprocessor, a 400-MHz 8-bit ASK-modulated RF transceiver, and two integrated dc-dc voltage converters for power management. This architecture exploits a low-power (sub 2-V) digital process for mixed-signal VLSI in a die size measuring 2.2 mm × 2.2 mm.

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U2 - 10.1109/GLSV.1999.757446

DO - 10.1109/GLSV.1999.757446

M3 - Conference contribution

AN - SCOPUS:0033361307

SN - 0769501044

T3 - Proceedings of the IEEE Great Lakes Symposium on VLSI

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BT - Proceedings of the IEEE Great Lakes Symposium on VLSI

PB - IEEE

T2 - Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)

Y2 - 4 March 1999 through 6 March 1999

ER -

Monolithic microprocessor and RF transceiver in 0.25-micron FDSOI CMOS

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