Monolithic 3D Integration of 2D Electronics based on Two-Dimensional Solid-Phase Crystallization

Chih Pin Lin, Yu Wei Kang, Chih Pin Hsu, Hao Hua Hsu, Jyun Hong Huang, Rui Fu Chen, Chien Tin Wu, Yao Jen Lee, Tuo-Hung Hou*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Monolithic 3D integration (M3D) of two-dimensional materials (2DMs) based on a device structure similar to the vertically stacked nanosheet (NS) gate-all-around (GAA) field-effect transistor (NS-GAAFET) is one of the most feasible paths for end-of-roadmap logic device scaling. A novel synthesis route, 2D solid-phase crystallization (2DSPC), is presented in this paper for M3D of 2DMs. 2DSPC presents a unique opportunity for achieving wafer-level uniformity, centimeter-scale monocrystalline grain, and scalable synthesis for multiple vertical layers. We believe 2DSPC offers a promising pathway toward future cost-effective M3D-2D electronics.

Original languageEnglish
Title of host publication2021 Symposium on VLSI Technology, VLSI Technology 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863487802
StatePublished - 2021
Event41st Symposium on VLSI Technology, VLSI Technology 2021 - Virtual, Online, Japan
Duration: 13 Jun 202119 Jun 2021

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2021-June
ISSN (Print)0743-1562

Conference

Conference41st Symposium on VLSI Technology, VLSI Technology 2021
Country/TerritoryJapan
CityVirtual, Online
Period13/06/2119/06/21

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