Monolithic 3D Integration of 2D Electronics based on Two-Dimensional Solid-Phase Crystallization

Chih Pin Lin; Yu Wei Kang; Chih Pin Hsu; Hao Hua Hsu; Jyun Hong Huang; Rui Fu Chen; Chien Tin Wu; Yao Jen Lee; Tuo-Hung Hou

Monolithic 3D Integration of 2D Electronics based on Two-Dimensional Solid-Phase Crystallization

Chih Pin Lin, Yu Wei Kang, Chih Pin Hsu, Hao Hua Hsu, Jyun Hong Huang, Rui Fu Chen, Chien Tin Wu, Yao Jen Lee, Tuo-Hung Hou^*

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Monolithic 3D integration (M3D) of two-dimensional materials (2DMs) based on a device structure similar to the vertically stacked nanosheet (NS) gate-all-around (GAA) field-effect transistor (NS-GAAFET) is one of the most feasible paths for end-of-roadmap logic device scaling. A novel synthesis route, 2D solid-phase crystallization (2DSPC), is presented in this paper for M3D of 2DMs. 2DSPC presents a unique opportunity for achieving wafer-level uniformity, centimeter-scale monocrystalline grain, and scalable synthesis for multiple vertical layers. We believe 2DSPC offers a promising pathway toward future cost-effective M3D-2D electronics.

Original language	English
Title of host publication	2021 Symposium on VLSI Technology, VLSI Technology 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863487802
State	Published - 2021
Event	41st Symposium on VLSI Technology, VLSI Technology 2021 - Virtual, Online, Japan Duration: 13 Jun 2021 → 19 Jun 2021

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2021-June
ISSN (Print)	0743-1562

Conference

Conference	41st Symposium on VLSI Technology, VLSI Technology 2021
Country/Territory	Japan
City	Virtual, Online
Period	13/06/21 → 19/06/21

Cite this

Lin, C. P., Kang, Y. W., Hsu, C. P., Hsu, H. H., Huang, J. H., Chen, R. F., Wu, C. T., Lee, Y. J., & Hou, T.-H. (2021). Monolithic 3D Integration of 2D Electronics based on Two-Dimensional Solid-Phase Crystallization. In 2021 Symposium on VLSI Technology, VLSI Technology 2021 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2021-June). Institute of Electrical and Electronics Engineers Inc..

@inproceedings{b878550284794ae886c240120ed55696,

title = "Monolithic 3D Integration of 2D Electronics based on Two-Dimensional Solid-Phase Crystallization",

abstract = "Monolithic 3D integration (M3D) of two-dimensional materials (2DMs) based on a device structure similar to the vertically stacked nanosheet (NS) gate-all-around (GAA) field-effect transistor (NS-GAAFET) is one of the most feasible paths for end-of-roadmap logic device scaling. A novel synthesis route, 2D solid-phase crystallization (2DSPC), is presented in this paper for M3D of 2DMs. 2DSPC presents a unique opportunity for achieving wafer-level uniformity, centimeter-scale monocrystalline grain, and scalable synthesis for multiple vertical layers. We believe 2DSPC offers a promising pathway toward future cost-effective M3D-2D electronics.",

author = "Lin, {Chih Pin} and Kang, {Yu Wei} and Hsu, {Chih Pin} and Hsu, {Hao Hua} and Huang, {Jyun Hong} and Chen, {Rui Fu} and Wu, {Chien Tin} and Lee, {Yao Jen} and Tuo-Hung Hou",

note = "Publisher Copyright: {\textcopyright} 2021 JSAP; 41st Symposium on VLSI Technology, VLSI Technology 2021 ; Conference date: 13-06-2021 Through 19-06-2021",

year = "2021",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2021 Symposium on VLSI Technology, VLSI Technology 2021",

address = "United States",

}

Lin, CP, Kang, YW, Hsu, CP, Hsu, HH, Huang, JH, Chen, RF, Wu, CT, Lee, YJ & Hou, T-H 2021, Monolithic 3D Integration of 2D Electronics based on Two-Dimensional Solid-Phase Crystallization. in 2021 Symposium on VLSI Technology, VLSI Technology 2021. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2021-June, Institute of Electrical and Electronics Engineers Inc., 41st Symposium on VLSI Technology, VLSI Technology 2021, Virtual, Online, Japan, 13/06/21.

Monolithic 3D Integration of 2D Electronics based on Two-Dimensional Solid-Phase Crystallization. / Lin, Chih Pin; Kang, Yu Wei; Hsu, Chih Pin et al.
2021 Symposium on VLSI Technology, VLSI Technology 2021. Institute of Electrical and Electronics Engineers Inc., 2021. (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2021-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Monolithic 3D Integration of 2D Electronics based on Two-Dimensional Solid-Phase Crystallization

AU - Lin, Chih Pin

AU - Kang, Yu Wei

AU - Hsu, Chih Pin

AU - Hsu, Hao Hua

AU - Huang, Jyun Hong

AU - Chen, Rui Fu

AU - Wu, Chien Tin

AU - Lee, Yao Jen

AU - Hou, Tuo-Hung

PY - 2021

Y1 - 2021

N2 - Monolithic 3D integration (M3D) of two-dimensional materials (2DMs) based on a device structure similar to the vertically stacked nanosheet (NS) gate-all-around (GAA) field-effect transistor (NS-GAAFET) is one of the most feasible paths for end-of-roadmap logic device scaling. A novel synthesis route, 2D solid-phase crystallization (2DSPC), is presented in this paper for M3D of 2DMs. 2DSPC presents a unique opportunity for achieving wafer-level uniformity, centimeter-scale monocrystalline grain, and scalable synthesis for multiple vertical layers. We believe 2DSPC offers a promising pathway toward future cost-effective M3D-2D electronics.

AB - Monolithic 3D integration (M3D) of two-dimensional materials (2DMs) based on a device structure similar to the vertically stacked nanosheet (NS) gate-all-around (GAA) field-effect transistor (NS-GAAFET) is one of the most feasible paths for end-of-roadmap logic device scaling. A novel synthesis route, 2D solid-phase crystallization (2DSPC), is presented in this paper for M3D of 2DMs. 2DSPC presents a unique opportunity for achieving wafer-level uniformity, centimeter-scale monocrystalline grain, and scalable synthesis for multiple vertical layers. We believe 2DSPC offers a promising pathway toward future cost-effective M3D-2D electronics.

UR - http://www.scopus.com/inward/record.url?scp=85125438177&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:85125438177

T3 - Digest of Technical Papers - Symposium on VLSI Technology

BT - 2021 Symposium on VLSI Technology, VLSI Technology 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 41st Symposium on VLSI Technology, VLSI Technology 2021

Y2 - 13 June 2021 through 19 June 2021

ER -

Monolithic 3D Integration of 2D Electronics based on Two-Dimensional Solid-Phase Crystallization

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