@inproceedings{84ff2c9934ed4458b7a922720f6387c5,
title = "Mixed-VTH (MVT) CMOS circuit design for low power cell libraries",
abstract = "Mixed-Vth (MVT) technique has been proposed to resize the MOS size and then reduce dynamic power in logic gates by applying a low threshold voltage to transistors in some critical paths, while a standard threshold voltage is used in non-critical paths. This paper presents 130nm and 90nm low power cell libraries using MVT technique. The dynamic power consumption of the cells has been reduced around 5% to 30% and with the same timing specifications.",
author = "Lin, {Jiun Yi} and Wang, {Li Rong} and Hu, {Chia Lin} and Shyh-Jye Jou",
year = "2007",
doi = "10.1109/SOCC.2007.4545454",
language = "English",
isbn = "9781424415922",
series = "Proceedings - 20th Anniversary IEEE International SOC Conference",
pages = "181--184",
booktitle = "Proceedings - 20th Anniversary IEEE International SOC Conference",
note = "20th Anniversary IEEE International SOC Conference ; Conference date: 26-09-2007 Through 29-09-2007",
}