Mixed-VTH (MVT) CMOS circuit design for low power cell libraries

Jiun Yi Lin; Li Rong Wang; Chia Lin Hu; Shyh-Jye Jou

doi:10.1109/SOCC.2007.4545454

Mixed-VTH (MVT) CMOS circuit design for low power cell libraries

Jiun Yi Lin^*, Li Rong Wang, Chia Lin Hu, Shyh-Jye Jou

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Mixed-Vth (MVT) technique has been proposed to resize the MOS size and then reduce dynamic power in logic gates by applying a low threshold voltage to transistors in some critical paths, while a standard threshold voltage is used in non-critical paths. This paper presents 130nm and 90nm low power cell libraries using MVT technique. The dynamic power consumption of the cells has been reduced around 5% to 30% and with the same timing specifications.

Original language	English
Title of host publication	Proceedings - 20th Anniversary IEEE International SOC Conference
Pages	181-184
Number of pages	4
DOIs	https://doi.org/10.1109/SOCC.2007.4545454
State	Published - 2007
Event	20th Anniversary IEEE International SOC Conference - Hsinchu, Taiwan Duration: 26 Sep 2007 → 29 Sep 2007

Publication series

Name	Proceedings - 20th Anniversary IEEE International SOC Conference

Conference

Conference	20th Anniversary IEEE International SOC Conference
Country/Territory	Taiwan
City	Hsinchu
Period	26/09/07 → 29/09/07

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10.1109/SOCC.2007.4545454

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@inproceedings{84ff2c9934ed4458b7a922720f6387c5,

title = "Mixed-VTH (MVT) CMOS circuit design for low power cell libraries",

abstract = "Mixed-Vth (MVT) technique has been proposed to resize the MOS size and then reduce dynamic power in logic gates by applying a low threshold voltage to transistors in some critical paths, while a standard threshold voltage is used in non-critical paths. This paper presents 130nm and 90nm low power cell libraries using MVT technique. The dynamic power consumption of the cells has been reduced around 5% to 30% and with the same timing specifications.",

author = "Lin, {Jiun Yi} and Wang, {Li Rong} and Hu, {Chia Lin} and Shyh-Jye Jou",

year = "2007",

doi = "10.1109/SOCC.2007.4545454",

language = "English",

isbn = "9781424415922",

series = "Proceedings - 20th Anniversary IEEE International SOC Conference",

pages = "181--184",

booktitle = "Proceedings - 20th Anniversary IEEE International SOC Conference",

note = "20th Anniversary IEEE International SOC Conference ; Conference date: 26-09-2007 Through 29-09-2007",

}

Lin, JY, Wang, LR, Hu, CL & Jou, S-J 2007, Mixed-VTH (MVT) CMOS circuit design for low power cell libraries. in Proceedings - 20th Anniversary IEEE International SOC Conference., 4545454, Proceedings - 20th Anniversary IEEE International SOC Conference, pp. 181-184, 20th Anniversary IEEE International SOC Conference, Hsinchu, Taiwan, 26/09/07. https://doi.org/10.1109/SOCC.2007.4545454

Mixed-VTH (MVT) CMOS circuit design for low power cell libraries. / Lin, Jiun Yi; Wang, Li Rong; Hu, Chia Lin et al.
Proceedings - 20th Anniversary IEEE International SOC Conference. 2007. p. 181-184 4545454 (Proceedings - 20th Anniversary IEEE International SOC Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lin, Jiun Yi

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AU - Hu, Chia Lin

AU - Jou, Shyh-Jye

PY - 2007

Y1 - 2007

N2 - Mixed-Vth (MVT) technique has been proposed to resize the MOS size and then reduce dynamic power in logic gates by applying a low threshold voltage to transistors in some critical paths, while a standard threshold voltage is used in non-critical paths. This paper presents 130nm and 90nm low power cell libraries using MVT technique. The dynamic power consumption of the cells has been reduced around 5% to 30% and with the same timing specifications.

AB - Mixed-Vth (MVT) technique has been proposed to resize the MOS size and then reduce dynamic power in logic gates by applying a low threshold voltage to transistors in some critical paths, while a standard threshold voltage is used in non-critical paths. This paper presents 130nm and 90nm low power cell libraries using MVT technique. The dynamic power consumption of the cells has been reduced around 5% to 30% and with the same timing specifications.

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SN - 9781424415922

T3 - Proceedings - 20th Anniversary IEEE International SOC Conference

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BT - Proceedings - 20th Anniversary IEEE International SOC Conference

T2 - 20th Anniversary IEEE International SOC Conference

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ER -

Mixed-VTH (MVT) CMOS circuit design for low power cell libraries

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