Mixed-VTH (MVT) CMOS circuit design for low power cell libraries

Jiun Yi Lin*, Li Rong Wang, Chia Lin Hu, Shyh-Jye Jou

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations

    Abstract

    Mixed-Vth (MVT) technique has been proposed to resize the MOS size and then reduce dynamic power in logic gates by applying a low threshold voltage to transistors in some critical paths, while a standard threshold voltage is used in non-critical paths. This paper presents 130nm and 90nm low power cell libraries using MVT technique. The dynamic power consumption of the cells has been reduced around 5% to 30% and with the same timing specifications.

    Original languageEnglish
    Title of host publicationProceedings - 20th Anniversary IEEE International SOC Conference
    Pages181-184
    Number of pages4
    DOIs
    StatePublished - 1 Dec 2007
    Event20th Anniversary IEEE International SOC Conference - Hsinchu, Taiwan
    Duration: 26 Sep 200729 Sep 2007

    Publication series

    NameProceedings - 20th Anniversary IEEE International SOC Conference

    Conference

    Conference20th Anniversary IEEE International SOC Conference
    Country/TerritoryTaiwan
    CityHsinchu
    Period26/09/0729/09/07

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