Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3×VDD input tolerance by using 1×VDD devices and single VDD supply

Ming-Dou Ker; Shih Lun Chen

doi:10.1109/ISSCC.2005.1494100

Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3×VDD input tolerance by using 1×VDD devices and single VDD supply

Ming-Dou Ker^*, Shih Lun Chen

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

20 Scopus citations

Abstract

This work presents a mixed-voltage I/O buffer realized with 1×V _DD devices and single V_DD power supply to receive 3×V_DD input signals without suffering gate-oxide reliability problems. The proposed I/O buffer is verified in a 0.13μm 1V CMOS process. This technique can be extended to receive 4×V_DD, 5×V _DD, and even 6×V_DD input signals.

Original language	English
Article number	28.8
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	48
DOIs	https://doi.org/10.1109/ISSCC.2005.1494100
State	Published - 6 Dec 2005
Event	2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: 6 Feb 2005 → 10 Feb 2005

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10.1109/ISSCC.2005.1494100

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@article{eb77432a3a7e468d915e8ebf16251342,

title = "Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3×VDD input tolerance by using 1×VDD devices and single VDD supply",

abstract = "This work presents a mixed-voltage I/O buffer realized with 1×V DD devices and single VDD power supply to receive 3×VDD input signals without suffering gate-oxide reliability problems. The proposed I/O buffer is verified in a 0.13μm 1V CMOS process. This technique can be extended to receive 4×VDD, 5×V DD, and even 6×VDD input signals.",

author = "Ming-Dou Ker and Chen, {Shih Lun}",

year = "2005",

month = dec,

day = "6",

doi = "10.1109/ISSCC.2005.1494100",

language = "English",

volume = "48",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2005 IEEE International Solid-State Circuits Conference, ISSCC ; Conference date: 06-02-2005 Through 10-02-2005",

}

TY - JOUR

T1 - Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3×VDD input tolerance by using 1×VDD devices and single VDD supply

AU - Ker, Ming-Dou

AU - Chen, Shih Lun

PY - 2005/12/6

Y1 - 2005/12/6

N2 - This work presents a mixed-voltage I/O buffer realized with 1×V DD devices and single VDD power supply to receive 3×VDD input signals without suffering gate-oxide reliability problems. The proposed I/O buffer is verified in a 0.13μm 1V CMOS process. This technique can be extended to receive 4×VDD, 5×V DD, and even 6×VDD input signals.

AB - This work presents a mixed-voltage I/O buffer realized with 1×V DD devices and single VDD power supply to receive 3×VDD input signals without suffering gate-oxide reliability problems. The proposed I/O buffer is verified in a 0.13μm 1V CMOS process. This technique can be extended to receive 4×VDD, 5×V DD, and even 6×VDD input signals.

UR - http://www.scopus.com/inward/record.url?scp=28144440292&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.2005.1494100

DO - 10.1109/ISSCC.2005.1494100

M3 - Conference article

AN - SCOPUS:28144443457

SN - 0193-6530

VL - 48

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

M1 - 28.8

T2 - 2005 IEEE International Solid-State Circuits Conference, ISSCC

Y2 - 6 February 2005 through 10 February 2005

ER -

Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3×VDD input tolerance by using 1×VDD devices and single VDD supply

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