This work presents a mixed-voltage I/O buffer realized with 1×V DD devices and single VDD power supply to receive 3×VDD input signals without suffering gate-oxide reliability problems. The proposed I/O buffer is verified in a 0.13μm 1V CMOS process. This technique can be extended to receive 4×VDD, 5×V DD, and even 6×VDD input signals.
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|State||Published - 6 Dec 2005|
|Event||2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States|
Duration: 6 Feb 2005 → 10 Feb 2005