Mixed signal design of cascadable matched filters

Chau-Chin Su; Hung Chi Lin; Shyh-Jye Jou

doi:10.1109/ISCAS.1997.621573

Mixed signal design of cascadable matched filters

Chau-Chin Su^*, Hung Chi Lin, Shyh-Jye Jou

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

Abstract

This paper presents the design, implementation, and test of a mixed signal matched filter. It uses simple current mirrors to reduce the complexity of the crucial summation circuit. The circuit is small in size and regular in structure. They can be cascaded into filters of longer length. A 128-chip test chip has been implemented in a 2.5 mm² core by 0.8 μm SPDM digital CMOS technology. The DC and AC measurement assert the feasibility of the design.

Original language	English
Pages (from-to)	2108-2111
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
DOIs	https://doi.org/10.1109/ISCAS.1997.621573
State	Published - 1 Jan 1997
Event	Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong Duration: 9 Jun 1997 → 12 Jun 1997

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10.1109/ISCAS.1997.621573

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title = "Mixed signal design of cascadable matched filters",

abstract = "This paper presents the design, implementation, and test of a mixed signal matched filter. It uses simple current mirrors to reduce the complexity of the crucial summation circuit. The circuit is small in size and regular in structure. They can be cascaded into filters of longer length. A 128-chip test chip has been implemented in a 2.5 mm2 core by 0.8 μm SPDM digital CMOS technology. The DC and AC measurement assert the feasibility of the design.",

author = "Chau-Chin Su and Lin, {Hung Chi} and Shyh-Jye Jou",

year = "1997",

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AU - Lin, Hung Chi

AU - Jou, Shyh-Jye

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Y1 - 1997/1/1

N2 - This paper presents the design, implementation, and test of a mixed signal matched filter. It uses simple current mirrors to reduce the complexity of the crucial summation circuit. The circuit is small in size and regular in structure. They can be cascaded into filters of longer length. A 128-chip test chip has been implemented in a 2.5 mm2 core by 0.8 μm SPDM digital CMOS technology. The DC and AC measurement assert the feasibility of the design.

AB - This paper presents the design, implementation, and test of a mixed signal matched filter. It uses simple current mirrors to reduce the complexity of the crucial summation circuit. The circuit is small in size and regular in structure. They can be cascaded into filters of longer length. A 128-chip test chip has been implemented in a 2.5 mm2 core by 0.8 μm SPDM digital CMOS technology. The DC and AC measurement assert the feasibility of the design.

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U2 - 10.1109/ISCAS.1997.621573

DO - 10.1109/ISCAS.1997.621573

M3 - Conference article

AN - SCOPUS:0030719795

VL - 3

SP - 2108

EP - 2111

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

Y2 - 9 June 1997 through 12 June 1997

ER -

Mixed signal design of cascadable matched filters

Abstract

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