Mismatch-tolerant time amplifier with embedded self-calibration

Jung Chin Lai*, Terng-Yin Hsu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

This paper presents a reliable self-calibration scheme to reduce the mismatches of SR-Latch based 6X time amplifier (TA) to enhance the resolution of time-to-digital converter (TDC). The proposed calibration is embedded to compensate for process, voltage and temperature (PVT) variations that it can eliminate the gain error caused by input mismatches. With the proposed TA, a standard cyclic TDC implemented in UMC 65-nm CMOS process shows that the resolution is 1.25ps.

Original languageEnglish
Title of host publication5th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2015
EditorsJose Maria Flores-Arias, Stefan Mozar, Dietmar Hepper, Milan Z. Bjelica, Hans L. Cycon
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages393-396
Number of pages4
ISBN (Electronic)9781479987481
DOIs
StatePublished - 25 Jan 2016
Event5th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2015 - Berlin, Germany
Duration: 6 Sep 20159 Sep 2015

Publication series

Name5th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2015

Conference

Conference5th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2015
Country/TerritoryGermany
CityBerlin
Period6/09/159/09/15

Keywords

  • Calibration
  • Mismatch
  • Reliable
  • TA
  • TDC

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