Mis-match characterization of 1.8V and 3.3V devices in 0.18μm mixed signal CMOS technology

T. H. Yeh*, J. C.H. Lin, S. C. Wong, H. Huang, J. Y.C. Sun

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

24 Scopus citations

Abstract

This paper studies the mis-match characteristics of 1.8V and 3.3V multiple threshold voltage devices, including nominal Vt, medium Vt and native devices in 0.18μm Mixed Signal CMOS technology for precision analog design. Three test structures, cross couple, stripe pair and parallel patterns, are presented to investigate the structure dependence mis-match behaviors. Matching characteristics of four analog parameters: Vt, Idsat, β and Gds, are investigated in terms of device size, layout configuration and process condition. Additional analytical model of current mis-match including Vt, β, source and drain series resistance and carrier velocity factor has been verified, in addition to global distortion of gate oxide thickness and substrate doping concentration.

Original languageEnglish
Pages77-82
Number of pages6
StatePublished - 2001
EventICMTS 2001. 2001 International Conference on Microelectronic Test Structures - Kobe, Japan
Duration: 19 Mar 200122 Mar 2001

Conference

ConferenceICMTS 2001. 2001 International Conference on Microelectronic Test Structures
Country/TerritoryJapan
CityKobe
Period19/03/0122/03/01

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