Metrology for analog module testing using analog testability bus

Chau-Chin Su*, Yue Tsang Chen, Shyh-Jye Jou, Yuan Tzu Ting

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

4 Scopus citations


In this paper, we propose a method to generate high quality test waveform on chip to avoid the parasitic effects in an analog testability bus test environment. For the test response analysis, we derive an extraction methodology to remove the parasitic effects and obtain the intrinsic response of the CUT. The test results show that the algorithm is robust such that the intrinsic responses remain the same regardless of the small variation in the test waveforms. With the concept of intrinsic responses, we are able to use a single library for the testing and diagnosis of multiple instantiation of an analog module.

Original languageEnglish
Article number5465474
Pages (from-to)594-599
Number of pages6
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
StatePublished - 1996
EventProceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA
Duration: 10 Nov 199614 Nov 1996


Dive into the research topics of 'Metrology for analog module testing using analog testability bus'. Together they form a unique fingerprint.

Cite this