Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology

Hsin Chyh Hsu; Chi Ming Chen; Ming-Dou Ker

doi:10.1109/VTSA.2005.1497064

Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology

Hsin Chyh Hsu^*, Chi Ming Chen, Ming-Dou Ker

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

NMOS with dummy-gate structure is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, the ESD current is discharged far away from the salicided surface channel of NMOS, therefore NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress.

Original language	English
Title of host publication	2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers
Pages	19-20
Number of pages	2
DOIs	https://doi.org/10.1109/VTSA.2005.1497064
State	Published - 31 Oct 2005
Event	2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH - Hsinchu, Taiwan Duration: 25 Apr 2005 → 27 Apr 2005

Publication series

Name	2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers

Conference

Conference	2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH
Country/Territory	Taiwan
City	Hsinchu
Period	25/04/05 → 27/04/05

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10.1109/VTSA.2005.1497064

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Hsu, H. C., Chen, C. M., & Ker, M-D. (2005). Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology. In 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers (pp. 19-20). [T13] (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers). https://doi.org/10.1109/VTSA.2005.1497064

Hsu, Hsin Chyh ; Chen, Chi Ming ; Ker, Ming-Dou. / Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology. 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers. 2005. pp. 19-20 (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers).

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title = "Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology",

abstract = "NMOS with dummy-gate structure is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, the ESD current is discharged far away from the salicided surface channel of NMOS, therefore NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress.",

author = "Hsu, {Hsin Chyh} and Chen, {Chi Ming} and Ming-Dou Ker",

year = "2005",

month = oct,

day = "31",

doi = "10.1109/VTSA.2005.1497064",

language = "English",

isbn = "078039058X",

series = "2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers",

pages = "19--20",

booktitle = "2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers",

note = "2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH ; Conference date: 25-04-2005 Through 27-04-2005",

}

Hsu, HC, Chen, CM & Ker, M-D 2005, Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology. in 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers., T13, 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers, pp. 19-20, 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Hsinchu, Taiwan, 25/04/05. https://doi.org/10.1109/VTSA.2005.1497064

Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology. / Hsu, Hsin Chyh; Chen, Chi Ming; Ker, Ming-Dou.
2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers. 2005. p. 19-20 T13 (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - NMOS with dummy-gate structure is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, the ESD current is discharged far away from the salicided surface channel of NMOS, therefore NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress.

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Hsu HC, Chen CM, Ker M-D. Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology. In 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers. 2005. p. 19-20. T13. (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers). doi: 10.1109/VTSA.2005.1497064

Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology

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