Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event

Tai Xiang Lai; Ming Dou Ker

doi:10.1109/EDSSC.2005.1635317

Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event

Tai Xiang Lai^*, Ming Dou Ker

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Cable Discharge Event (CDE) has been the main cause which damages the Ethernet interface. The transmission line pulsing (TLP) system has been the most important method to observe electric characteristics of the device under human-body-model (HBM) ESD stress. In this work, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of CDE on the Ethernet integrated circuits, and the results are compared with conventional 100-ns TLP system. The experimental results have shown that the CDE robustness of NMOS device in a 0.25-μm CMOS technology is much worse than its HBM electrostatic discharge robustness.

Original language	English
Title of host publication	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	499-502
Number of pages	4
ISBN (Print)	0780393392, 9780780393394
DOIs	https://doi.org/10.1109/EDSSC.2005.1635317
State	Published - 2005
Event	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC - Howloon, Hong Kong Duration: 19 Dec 2005 → 21 Dec 2005

Publication series

Name	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

Conference

Conference	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
Country/Territory	Hong Kong
City	Howloon
Period	19/12/05 → 21/12/05

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10.1109/EDSSC.2005.1635317

Cite this

Lai, T. X., & Ker, M. D. (2005). Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event. In 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC (pp. 499-502). Article 1635317 (2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2005.1635317

@inproceedings{be2e473bc6c34c05b1faf1c4907699e1,

title = "Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event",

abstract = "Cable Discharge Event (CDE) has been the main cause which damages the Ethernet interface. The transmission line pulsing (TLP) system has been the most important method to observe electric characteristics of the device under human-body-model (HBM) ESD stress. In this work, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of CDE on the Ethernet integrated circuits, and the results are compared with conventional 100-ns TLP system. The experimental results have shown that the CDE robustness of NMOS device in a 0.25-μm CMOS technology is much worse than its HBM electrostatic discharge robustness.",

author = "Lai, {Tai Xiang} and Ker, {Ming Dou}",

year = "2005",

doi = "10.1109/EDSSC.2005.1635317",

language = "English",

isbn = "0780393392",

series = "2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "499--502",

booktitle = "2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC",

address = "美國",

note = "2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC ; Conference date: 19-12-2005 Through 21-12-2005",

}

Lai, TX & Ker, MD 2005, Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event. in 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC., 1635317, 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC, Institute of Electrical and Electronics Engineers Inc., pp. 499-502, 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC, Howloon, Hong Kong, 19/12/05. https://doi.org/10.1109/EDSSC.2005.1635317

Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event. / Lai, Tai Xiang; Ker, Ming Dou.
2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC. Institute of Electrical and Electronics Engineers Inc., 2005. p. 499-502 1635317 (2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lai, Tai Xiang

AU - Ker, Ming Dou

PY - 2005

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N2 - Cable Discharge Event (CDE) has been the main cause which damages the Ethernet interface. The transmission line pulsing (TLP) system has been the most important method to observe electric characteristics of the device under human-body-model (HBM) ESD stress. In this work, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of CDE on the Ethernet integrated circuits, and the results are compared with conventional 100-ns TLP system. The experimental results have shown that the CDE robustness of NMOS device in a 0.25-μm CMOS technology is much worse than its HBM electrostatic discharge robustness.

AB - Cable Discharge Event (CDE) has been the main cause which damages the Ethernet interface. The transmission line pulsing (TLP) system has been the most important method to observe electric characteristics of the device under human-body-model (HBM) ESD stress. In this work, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of CDE on the Ethernet integrated circuits, and the results are compared with conventional 100-ns TLP system. The experimental results have shown that the CDE robustness of NMOS device in a 0.25-μm CMOS technology is much worse than its HBM electrostatic discharge robustness.

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DO - 10.1109/EDSSC.2005.1635317

M3 - Conference contribution

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SN - 0780393392

SN - 9780780393394

T3 - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

SP - 499

EP - 502

BT - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

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Lai TX, Ker MD. Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event. In 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC. Institute of Electrical and Electronics Engineers Inc. 2005. p. 499-502. 1635317. (2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC). doi: 10.1109/EDSSC.2005.1635317

Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event

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