@inproceedings{90a125d1f7a542c0bc4fdd2b1c358ec5,
title = "Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation",
abstract = "This work proposes a novel Dual-Port (DP) 8T SRAM operation scheme. The scheme improves the Read stability and Write-ability, and allows asynchronous operation with arbitrary clock timing skew between two ports. It facilitates high performance, low-power and low VMIN with minimum device and area overhead. Post-simulation results show almost no timing penalty for simultaneous same-row access and the performance is almost the same as that for one port operation.",
author = "Lien, {Nan Chun} and Chuang, {Ching Te} and Wen-Rong Wu",
year = "2013",
month = jan,
day = "1",
doi = "10.1109/SOCC.2013.6749669",
language = "English",
isbn = "9781479911660",
series = "International System on Chip Conference",
publisher = "IEEE Computer Society",
pages = "105--109",
booktitle = "Proceedings - IEEE 26th International SOC Conference, SOCC 2013",
address = "United States",
note = "26th IEEE International System-on-Chip Conference, SOCC 2013 ; Conference date: 04-09-2013 Through 06-09-2013",
}