Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM

Deep neural networks require enormous computation capacity, great amounts of data accesses from memory and data movement among processing elements (PEs). In fact, data access energy costs on the data access exceed that of computation. Therefore, managing data reuse efficiently and reducing data movement have become the critical design issues. In this paper, an energy-efficient fusion-based DNN is proposed based on a 3D scalable network-on-chip (NoC) with vertical 3D stacked memory to reduce large memory footprints. The effective reuse of data through this approach reduces the data access and energy consumption over current 2D-DRAM designs. A high-efficiency data flow with pipeline, which can process more data in parallel, is also proposed for increasing the resource utilization. Additionally, dynamic voltage/frequency scaling (DVFS) for 3D memory interface and a prefetch technique are utilized into distributed vault controllers to improve system efficiency. Overall, the proposed fusion-based 3D NoC with 3D-DRAM decreases the energy-delay product (EDP) up to 148x compared to conventional NoC with 2D baseline DDR3.