Memory-based approach to the design of efficient VLSI arrays for the multi-dimensional discrete Hartley transform

Keyphrases

• Very Large Scale Integration 100%
• Memory-based 100%
• Discrete Hartley Transform 100%
• Cyclic Convolution 40%
• Systolic Array 40%
• Function Unit 40%
• Hardware Efficiency 20%
• Parallelization 20%
• Design Approach 20%
• Input-output 20%
• Low Computational Complexity 20%
• Hardware Cost 20%
• Implementation Scheme 20%
• Distributed Arithmetic 20%
• Low Input 20%
• Computing Speed 20%
• Read Only Memory 20%
• Output Costs 20%
• Very Large Scale Integration (VLSI) Architecture 20%

Engineering

• VLSI Circuits 100%
• Dimensional Discrete 100%
• Hartley 100%
• Systolic Arrays 33%
• Cyclic Convolution 33%
• Parallelism 16%
• Adders 16%
• Realization 16%
• Hardware Cost 16%
• Computation Complexity 16%

Computer Science

• Dimensional Discrete 100%
• Very Large Scale Integration 100%
• Cyclic Convolution 40%
• Systolic Arrays 40%
• Input/Output 20%
• Computation Complexity 20%
• Hardware Cost 20%
• Presented Approach 20%
• Parallel Computing 20%
• Very large-scale integration (VLSI) architecture 20%
• Read Only Memory 20%
• Computer Hardware 20%