Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits

Jen Chou Tseng; Yu Lin Chen; Chung Ti Hsu; Fu Yi Tsai; Po An Chen; Ming-Dou Ker

doi:10.1109/RELPHY.2008.4558958

Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits

Jen Chou Tseng^*, Yu Lin Chen, Chung Ti Hsu, Fu Yi Tsai, Po An Chen, Ming-Dou Ker

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

An electrical overstress failure induced by a latch-up test is studied in high-voltage integrated circuits. The latchup test resulted in damage to the output NMOSFET due to snapback and also resulted in a latchup in the internal circuits. These mechanisms are analyzed and solutions are proposed to avoid the triggering of the output NMOSFET and the resulting latchup issue.

Original language	English
Title of host publication	46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS
Pages	625-626
Number of pages	2
DOIs	https://doi.org/10.1109/RELPHY.2008.4558958
State	Published - 17 Sep 2008
Event	46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS - Phoenix, AZ, United States Duration: 27 Apr 2008 → 1 May 2008

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
ISSN (Print)	1541-7026

Conference

Conference	46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS
Country/Territory	United States
City	Phoenix, AZ
Period	27/04/08 → 1/05/08

Keywords

EOS
ESD
High-voltage
Latch-up

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10.1109/RELPHY.2008.4558958

Cite this

Tseng, J. C., Chen, Y. L., Hsu, C. T., Tsai, F. Y., Chen, P. A., & Ker, M.-D. (2008). Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits. In 46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS (pp. 625-626). Article 4558958 (IEEE International Reliability Physics Symposium Proceedings). https://doi.org/10.1109/RELPHY.2008.4558958

@inproceedings{5aee363b0b6f4e4e9e8d403f664e8c31,

title = "Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits",

abstract = "An electrical overstress failure induced by a latch-up test is studied in high-voltage integrated circuits. The latchup test resulted in damage to the output NMOSFET due to snapback and also resulted in a latchup in the internal circuits. These mechanisms are analyzed and solutions are proposed to avoid the triggering of the output NMOSFET and the resulting latchup issue.",

keywords = "EOS, ESD, High-voltage, Latch-up",

author = "Tseng, {Jen Chou} and Chen, {Yu Lin} and Hsu, {Chung Ti} and Tsai, {Fu Yi} and Chen, {Po An} and Ming-Dou Ker",

year = "2008",

month = sep,

day = "17",

doi = "10.1109/RELPHY.2008.4558958",

language = "English",

isbn = "9781424420506",

series = "IEEE International Reliability Physics Symposium Proceedings",

pages = "625--626",

booktitle = "46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS",

note = "46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS ; Conference date: 27-04-2008 Through 01-05-2008",

}

Tseng, JC, Chen, YL, Hsu, CT, Tsai, FY, Chen, PA & Ker, M-D 2008, Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits. in 46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS., 4558958, IEEE International Reliability Physics Symposium Proceedings, pp. 625-626, 46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS, Phoenix, AZ, United States, 27/04/08. https://doi.org/10.1109/RELPHY.2008.4558958

Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits. / Tseng, Jen Chou; Chen, Yu Lin; Hsu, Chung Ti et al.
46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS. 2008. p. 625-626 4558958 (IEEE International Reliability Physics Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits

AU - Tseng, Jen Chou

AU - Chen, Yu Lin

AU - Hsu, Chung Ti

AU - Tsai, Fu Yi

AU - Chen, Po An

AU - Ker, Ming-Dou

PY - 2008/9/17

Y1 - 2008/9/17

N2 - An electrical overstress failure induced by a latch-up test is studied in high-voltage integrated circuits. The latchup test resulted in damage to the output NMOSFET due to snapback and also resulted in a latchup in the internal circuits. These mechanisms are analyzed and solutions are proposed to avoid the triggering of the output NMOSFET and the resulting latchup issue.

AB - An electrical overstress failure induced by a latch-up test is studied in high-voltage integrated circuits. The latchup test resulted in damage to the output NMOSFET due to snapback and also resulted in a latchup in the internal circuits. These mechanisms are analyzed and solutions are proposed to avoid the triggering of the output NMOSFET and the resulting latchup issue.

KW - EOS

KW - ESD

KW - High-voltage

KW - Latch-up

UR - http://www.scopus.com/inward/record.url?scp=51549109991&partnerID=8YFLogxK

U2 - 10.1109/RELPHY.2008.4558958

DO - 10.1109/RELPHY.2008.4558958

M3 - Conference contribution

AN - SCOPUS:51549109991

SN - 9781424420506

T3 - IEEE International Reliability Physics Symposium Proceedings

SP - 625

EP - 626

BT - 46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS

T2 - 46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS

Y2 - 27 April 2008 through 1 May 2008

ER -

Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits

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Keywords

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