TY - GEN
T1 - Mathematical yield estimation for two-dimensional-redundancy memory arrays
AU - Chao, Chia-Tso
AU - Chin, Ching Yu
AU - Lin, Chen Wei
PY - 2010
Y1 - 2010
N2 - Defect repair has become a necessary process to enhance the overall yield for memories since manufacturing a natural good memory is difficult in current memory technologies. This paper presents an yield-estimation scheme, which utilizes an inductionbased approach to calculate the probability that all defects in a memory can be successfully repaired by a two-dimensional redundancy design. Unlike previous works, which rely on a timeconsuming simulation to estimate the expected yield, our yieldestimation scheme only requires scalable mathematical computation and can achieve a high accuracy with limited time and space complexity. Also, the proposed estimation scheme can consider the impact of single defects, column defects, and row defects simultaneously. With the help of the proposed yield-estimation scheme, we can effectively identify the most profitable redundancy configuration for large memory designs within few seconds while it may take several hours or even days by using conventional simulation approach.
AB - Defect repair has become a necessary process to enhance the overall yield for memories since manufacturing a natural good memory is difficult in current memory technologies. This paper presents an yield-estimation scheme, which utilizes an inductionbased approach to calculate the probability that all defects in a memory can be successfully repaired by a two-dimensional redundancy design. Unlike previous works, which rely on a timeconsuming simulation to estimate the expected yield, our yieldestimation scheme only requires scalable mathematical computation and can achieve a high accuracy with limited time and space complexity. Also, the proposed estimation scheme can consider the impact of single defects, column defects, and row defects simultaneously. With the help of the proposed yield-estimation scheme, we can effectively identify the most profitable redundancy configuration for large memory designs within few seconds while it may take several hours or even days by using conventional simulation approach.
UR - http://www.scopus.com/inward/record.url?scp=78650893595&partnerID=8YFLogxK
U2 - 10.1109/ICCAD.2010.5654154
DO - 10.1109/ICCAD.2010.5654154
M3 - Conference contribution
AN - SCOPUS:78650893595
SN - 9781424481927
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 235
EP - 240
BT - 2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
Y2 - 7 November 2010 through 11 November 2010
ER -