Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters

Pang Yen Chou, Nai Chen Chen, Po-Hung Lin, Helmut Graeb

Research output: Contribution to journalArticlepeer-review

6 Scopus citations


As technology advances, smaller feature size enables layout precision in the lateral direction. In contrast to traditional metal-insulator-metal capacitors, metal-oxide-metal (MOM) capacitors are generally of higher density and consume less area, because they adopt a 3-D topology over several metal layers to use lateral field capacitance. To achieve little area consumption, MOM capacitors require new layout methods with routing even before placement. Since the routing wires are of comparable size to unit capacitors in MOM design, routing-induced parasitic capacitance must also be considered. To obtain a higher yield, common-centroid layout style and high dispersion of cells are desired. This paper introduces a new vertical bars structure for binary weighted MOM capacitor arrays and presents a new method to generate common-centroid regular-structured layouts with mismatch reduction and routing-parasitic-matching consideration. Experimental results show that the presented approach generates high-density, low-powered, and highly accurate ratioed capacitors.

Original languageEnglish
Article number7896631
Pages (from-to)2234-2247
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number8
StatePublished - 1 Aug 2017


  • Analog
  • automation
  • capacitor
  • design
  • layout


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