MapReduce-based pattern classification for design space analysis

Yan Shiun Wu; Hong Yan Su; Yi Hsiang Chang; Rasit Onur Topaloglu; Yih-Lang Li

doi:10.1109/VLSI-DAT.2018.8373275

MapReduce-based pattern classification for design space analysis

Yan Shiun Wu, Hong Yan Su, Yi Hsiang Chang, Rasit Onur Topaloglu, Yih-Lang Li

Institute of Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

With the ongoing reduction of feature size, design for manufacturability is a critical concern in advanced technology nodes. Pattern classification is a promising and widely employed approach for design space analysis, design rule generation, and yield optimization. In this paper, we propose a hybrid algorithm that account for two variations for classification metrics: feature edge displacement and total feature area difference. A MapRe-duce-based framework is proposed to reduce the complexity of the pattern classification problem such that orders of magnitude of performance improvement can be realized. Our experimental results indicate that regarding accuracy and runtime, this work out-performs the winner of the CAD Contest at ICCAD 2016 in terms of contest scoring measure.

Original language	English
Title of host publication	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-4
Number of pages	4
ISBN (Electronic)	9781538642603
DOIs	https://doi.org/10.1109/VLSI-DAT.2018.8373275
State	Published - 5 Jun 2018
Event	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan Duration: 16 Apr 2018 → 19 Apr 2018

Publication series

Name	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

Conference

Conference	2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Country/Territory	Taiwan
City	Hsinchu
Period	16/04/18 → 19/04/18

Keywords

MapReduce
Prüfer encoding
design for manufacturability
pattern classification

Access to Document

10.1109/VLSI-DAT.2018.8373275

Cite this

Wu, Y. S., Su, H. Y., Chang, Y. H., Topaloglu, R. O., & Li, Y.-L. (2018). MapReduce-based pattern classification for design space analysis. In 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 (pp. 1-4). (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2018.8373275

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title = "MapReduce-based pattern classification for design space analysis",

abstract = "With the ongoing reduction of feature size, design for manufacturability is a critical concern in advanced technology nodes. Pattern classification is a promising and widely employed approach for design space analysis, design rule generation, and yield optimization. In this paper, we propose a hybrid algorithm that account for two variations for classification metrics: feature edge displacement and total feature area difference. A MapRe-duce-based framework is proposed to reduce the complexity of the pattern classification problem such that orders of magnitude of performance improvement can be realized. Our experimental results indicate that regarding accuracy and runtime, this work out-performs the winner of the CAD Contest at ICCAD 2016 in terms of contest scoring measure.",

keywords = "MapReduce, Pr{\"u}fer encoding, design for manufacturability, pattern classification",

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year = "2018",

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doi = "10.1109/VLSI-DAT.2018.8373275",

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booktitle = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018",

address = "美國",

note = "2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 ; Conference date: 16-04-2018 Through 19-04-2018",

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Wu, YS, Su, HY, Chang, YH, Topaloglu, RO & Li, Y-L 2018, MapReduce-based pattern classification for design space analysis. in 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, Hsinchu, Taiwan, 16/04/18. https://doi.org/10.1109/VLSI-DAT.2018.8373275

MapReduce-based pattern classification for design space analysis. / Wu, Yan Shiun; Su, Hong Yan; Chang, Yi Hsiang et al.
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4 (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - With the ongoing reduction of feature size, design for manufacturability is a critical concern in advanced technology nodes. Pattern classification is a promising and widely employed approach for design space analysis, design rule generation, and yield optimization. In this paper, we propose a hybrid algorithm that account for two variations for classification metrics: feature edge displacement and total feature area difference. A MapRe-duce-based framework is proposed to reduce the complexity of the pattern classification problem such that orders of magnitude of performance improvement can be realized. Our experimental results indicate that regarding accuracy and runtime, this work out-performs the winner of the CAD Contest at ICCAD 2016 in terms of contest scoring measure.

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Wu YS, Su HY, Chang YH, Topaloglu RO, Li YL. MapReduce-based pattern classification for design space analysis. In 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-4. (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018). doi: 10.1109/VLSI-DAT.2018.8373275

MapReduce-based pattern classification for design space analysis

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