Low-voltage low-power IF-baseband digital down converter

Shyh-Jye Jou; Tsan I. Hsu; C. K. Wang

doi:10.1109/VTSA.1997.614773

Low-voltage low-power IF-baseband digital down converter

Shyh-Jye Jou^*, Tsan I. Hsu, C. K. Wang

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

Abstract

A low-voltage low-power all digital down converter (ADDC) is presented for implementing the IF front end signal processing. The ADDC chip accepts a 5-bits digitized intermediate-frequency (IF) input signal and generates a pair of 10-bits filtered in-phase and quadrature baseband signals. Low power consumption is main design consideration in this ADDC chip. Thus, many low power design technologies that include algorithm, architecture and circuit level are used to keep the power dissipation minimum. The ADDC has a symbol rate of 1.2288 MHz (clock rate 19.6608 MHz) and 1 mW average power dissipation when operated in 2 V power supply. The chip was fabricated in a 0.8 μm single poly double metal CMOS process. The core area is 2.45 mm² and is composed of 12,100 transistors.

Original language	English
Pages	270-274
Number of pages	5
DOIs	https://doi.org/10.1109/VTSA.1997.614773
State	Published - 1997
Event	Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China Duration: 3 Jun 1997 → 5 Jun 1997

Conference

Conference	Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications
City	Taipei, China
Period	3/06/97 → 5/06/97

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10.1109/VTSA.1997.614773

Cite this

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title = "Low-voltage low-power IF-baseband digital down converter",

abstract = "A low-voltage low-power all digital down converter (ADDC) is presented for implementing the IF front end signal processing. The ADDC chip accepts a 5-bits digitized intermediate-frequency (IF) input signal and generates a pair of 10-bits filtered in-phase and quadrature baseband signals. Low power consumption is main design consideration in this ADDC chip. Thus, many low power design technologies that include algorithm, architecture and circuit level are used to keep the power dissipation minimum. The ADDC has a symbol rate of 1.2288 MHz (clock rate 19.6608 MHz) and 1 mW average power dissipation when operated in 2 V power supply. The chip was fabricated in a 0.8 μm single poly double metal CMOS process. The core area is 2.45 mm2 and is composed of 12,100 transistors.",

author = "Shyh-Jye Jou and Hsu, {Tsan I.} and Wang, {C. K.}",

year = "1997",

doi = "10.1109/VTSA.1997.614773",

language = "English",

pages = "270--274",

note = "Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications ; Conference date: 03-06-1997 Through 05-06-1997",

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TY - CONF

T1 - Low-voltage low-power IF-baseband digital down converter

AU - Jou, Shyh-Jye

AU - Hsu, Tsan I.

AU - Wang, C. K.

PY - 1997

Y1 - 1997

N2 - A low-voltage low-power all digital down converter (ADDC) is presented for implementing the IF front end signal processing. The ADDC chip accepts a 5-bits digitized intermediate-frequency (IF) input signal and generates a pair of 10-bits filtered in-phase and quadrature baseband signals. Low power consumption is main design consideration in this ADDC chip. Thus, many low power design technologies that include algorithm, architecture and circuit level are used to keep the power dissipation minimum. The ADDC has a symbol rate of 1.2288 MHz (clock rate 19.6608 MHz) and 1 mW average power dissipation when operated in 2 V power supply. The chip was fabricated in a 0.8 μm single poly double metal CMOS process. The core area is 2.45 mm2 and is composed of 12,100 transistors.

AB - A low-voltage low-power all digital down converter (ADDC) is presented for implementing the IF front end signal processing. The ADDC chip accepts a 5-bits digitized intermediate-frequency (IF) input signal and generates a pair of 10-bits filtered in-phase and quadrature baseband signals. Low power consumption is main design consideration in this ADDC chip. Thus, many low power design technologies that include algorithm, architecture and circuit level are used to keep the power dissipation minimum. The ADDC has a symbol rate of 1.2288 MHz (clock rate 19.6608 MHz) and 1 mW average power dissipation when operated in 2 V power supply. The chip was fabricated in a 0.8 μm single poly double metal CMOS process. The core area is 2.45 mm2 and is composed of 12,100 transistors.

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U2 - 10.1109/VTSA.1997.614773

DO - 10.1109/VTSA.1997.614773

M3 - Paper

AN - SCOPUS:0030653182

SP - 270

EP - 274

T2 - Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications

Y2 - 3 June 1997 through 5 June 1997

ER -

Low-voltage low-power IF-baseband digital down converter

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