Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

Chun Chiang; Ping Chen Chang; Mei Ling Chao; Tien Hao Tang; Kuan Cheng Su; Ming-Dou Ker

doi:10.1109/IPFA.2017.8060226

Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

Chun Chiang, Ping Chen Chang, Mei Ling Chao, Tien Hao Tang, Kuan Cheng Su, Ming-Dou Ker

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (V_BD) and low holding voltage (V_h) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM<8kV) and good turn-on efficiency (V_t1=8.1V) without suffering from low V_BD and latch-up issues.

Original language	English
Title of host publication	24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-3
Number of pages	3
ISBN (Electronic)	9781538617793
DOIs	https://doi.org/10.1109/IPFA.2017.8060226
State	Published - 5 Oct 2017
Event	24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017 - Chengdu, China Duration: 4 Jul 2017 → 7 Jul 2017

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume	2017-July

Conference

Conference	24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
Country/Territory	China
City	Chengdu
Period	4/07/17 → 7/07/17

Access to Document

10.1109/IPFA.2017.8060226

Cite this

Chiang, C., Chang, P. C., Chao, M. L., Tang, T. H., Su, K. C., & Ker, M-D. (2017). Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering. In 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017 (pp. 1-3). (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; Vol. 2017-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPFA.2017.8060226

Chiang, Chun ; Chang, Ping Chen ; Chao, Mei Ling et al. / Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering. 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 1-3 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

@inproceedings{9c68d1b849644cc6a0ae001cc9ae2c79,

title = "Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering",

abstract = "According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (VBD) and low holding voltage (Vh) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM<8kV) and good turn-on efficiency (Vt1=8.1V) without suffering from low VBD and latch-up issues.",

author = "Chun Chiang and Chang, {Ping Chen} and Chao, {Mei Ling} and Tang, {Tien Hao} and Su, {Kuan Cheng} and Ming-Dou Ker",

year = "2017",

month = oct,

day = "5",

doi = "10.1109/IPFA.2017.8060226",

language = "English",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--3",

booktitle = "24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017",

address = "United States",

note = "null ; Conference date: 04-07-2017 Through 07-07-2017",

}

Chiang, C, Chang, PC, Chao, ML, Tang, TH, Su, KC & Ker, M-D 2017, Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering. in 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017. Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, vol. 2017-July, Institute of Electrical and Electronics Engineers Inc., pp. 1-3, 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017, Chengdu, China, 4/07/17. https://doi.org/10.1109/IPFA.2017.8060226

Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering. / Chiang, Chun; Chang, Ping Chen; Chao, Mei Ling et al.

24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 1-3 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; Vol. 2017-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chang, Ping Chen

AU - Chao, Mei Ling

AU - Tang, Tien Hao

AU - Su, Kuan Cheng

AU - Ker, Ming-Dou

PY - 2017/10/5

Y1 - 2017/10/5

N2 - According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (VBD) and low holding voltage (Vh) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM<8kV) and good turn-on efficiency (Vt1=8.1V) without suffering from low VBD and latch-up issues.

AB - According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (VBD) and low holding voltage (Vh) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM<8kV) and good turn-on efficiency (Vt1=8.1V) without suffering from low VBD and latch-up issues.

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M3 - Conference contribution

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Chiang C, Chang PC, Chao ML, Tang TH, Su KC, Ker M-D. Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering. In 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 1-3. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2017.8060226

Low-Trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

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