TY - GEN
T1 - Low thermal budget amorphous indium tungsten oxide nano-sheet junctionless transistors with near ideal subthreshold swing
AU - Kuo, Po Yi
AU - Chang, Chien Min
AU - Liu, Po-Tsun
PY - 2018/6
Y1 - 2018/6
N2 -
Amorphous indium tungsten oxide (a-IWO) nano-sheet (NS) junctionless (JL) transistors (a-IWO NS-JLTs) have been successfully fabricated and demonstrated in the category of indium oxide based thin film transistors (TFTs). We have scaled down thickness of a-IWO channel to 4nm. The proposed a-IWO NS-JLTs with low operation voltages exhibit good electrical characteristics: near ideal peak subthreshold swing (S.S.) ∼ 63mV/dec., high field-effect mobility (μ
FE
) ∼ 25.3 cm
2
/V-s. The novel a-IWO NS-JLTs with low temperature processes are promising candidates for monolithic three-dimensional integrated circuits (3-D ICs), vertical stacked (VS) hybrid CMOS technology, and large-scale integration (LSI) applications in the future.
AB -
Amorphous indium tungsten oxide (a-IWO) nano-sheet (NS) junctionless (JL) transistors (a-IWO NS-JLTs) have been successfully fabricated and demonstrated in the category of indium oxide based thin film transistors (TFTs). We have scaled down thickness of a-IWO channel to 4nm. The proposed a-IWO NS-JLTs with low operation voltages exhibit good electrical characteristics: near ideal peak subthreshold swing (S.S.) ∼ 63mV/dec., high field-effect mobility (μ
FE
) ∼ 25.3 cm
2
/V-s. The novel a-IWO NS-JLTs with low temperature processes are promising candidates for monolithic three-dimensional integrated circuits (3-D ICs), vertical stacked (VS) hybrid CMOS technology, and large-scale integration (LSI) applications in the future.
UR - http://www.scopus.com/inward/record.url?scp=85056851125&partnerID=8YFLogxK
U2 - 10.1109/VLSIT.2018.8510684
DO - 10.1109/VLSIT.2018.8510684
M3 - Conference contribution
AN - SCOPUS:85056851125
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 21
EP - 22
BT - 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
Y2 - 18 June 2018 through 22 June 2018
ER -