Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode

Shiyang Zhu; H. Y. Yu; J. D. Chen; S. J. Whang; J. H. Chen; Chen Shen; Chunxiang Zhu; S. J. Lee; M. F. Li; D. S.H. Chan; W. J. Yoo; Anyan Du; C. H. Tung; Jagar Singh; Albert Chin; D. L. Kwong

doi:10.1016/j.sse.2004.05.045

Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode

Shiyang Zhu, H. Y. Yu, J. D. Chen, S. J. Whang, J. H. Chen, Chen Shen, Chunxiang Zhu, S. J. Lee, M. F. Li^*, D. S.H. Chan, W. J. Yoo, Anyan Du, C. H. Tung, Jagar Singh, Albert Chin, D. L. Kwong

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

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Abstract

Both P- and N-channel MOSFETs with Schottky barrier silicide source/drain (S/D), high-K gate dielectric and metal gate were successfully fabricated using a simplified low temperature process. The highest temperature after the high-K dielectric formation is 420°C. PMOSFETs with PtSi S/D show excellent electrical performance of an I_on/I_off ∼ 10 ⁷-10⁸ and a subthreshold slope of 66 mV/dec, similar to those formed by a normal process with an optimized sidewall spacer. NMOSFETs with DySi_2-x S/D have ∼3 orders of magnitude larger I _off than that of PMOSFETs and show two slopes in the subthreshold region, resulting in the I_on/I_off ∼ 10⁵ at low drain voltage. It can be attributed to the relatively higher barrier height (Φ_n) of DySi_2-x/n-Si than that of PtSi/p-Si (Φ_p) and the rougher DySi_2-x film. Adding a thin intermediate Ge layer (∼1 nm) between Dy and Si can improve the film morphology significantly. As a result, the improved performance of N-MOSFET is observed.

Original language	English
Pages (from-to)	1987-1992
Number of pages	6
Journal	Solid-State Electronics
Volume	48
Issue number	10-11 SPEC. ISS.
DOIs	https://doi.org/10.1016/j.sse.2004.05.045
State	Published - 1 Oct 2004

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Zhu, S., Yu, H. Y., Chen, J. D., Whang, S. J., Chen, J. H., Shen, C., Zhu, C., Lee, S. J., Li, M. F., Chan, D. S. H., Yoo, W. J., Du, A., Tung, C. H., Singh, J., Chin, A., & Kwong, D. L. (2004). Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode. Solid-State Electronics, 48(10-11 SPEC. ISS.), 1987-1992. https://doi.org/10.1016/j.sse.2004.05.045

@article{ddf0bad02b784739a349f91ee1e18d05,

title = "Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode",

abstract = "Both P- and N-channel MOSFETs with Schottky barrier silicide source/drain (S/D), high-K gate dielectric and metal gate were successfully fabricated using a simplified low temperature process. The highest temperature after the high-K dielectric formation is 420°C. PMOSFETs with PtSi S/D show excellent electrical performance of an Ion/Ioff ∼ 10 7-108 and a subthreshold slope of 66 mV/dec, similar to those formed by a normal process with an optimized sidewall spacer. NMOSFETs with DySi2-x S/D have ∼3 orders of magnitude larger I off than that of PMOSFETs and show two slopes in the subthreshold region, resulting in the Ion/Ioff ∼ 105 at low drain voltage. It can be attributed to the relatively higher barrier height (Φn) of DySi2-x/n-Si than that of PtSi/p-Si (Φp) and the rougher DySi2-x film. Adding a thin intermediate Ge layer (∼1 nm) between Dy and Si can improve the film morphology significantly. As a result, the improved performance of N-MOSFET is observed.",

author = "Shiyang Zhu and Yu, {H. Y.} and Chen, {J. D.} and Whang, {S. J.} and Chen, {J. H.} and Chen Shen and Chunxiang Zhu and Lee, {S. J.} and Li, {M. F.} and Chan, {D. S.H.} and Yoo, {W. J.} and Anyan Du and Tung, {C. H.} and Jagar Singh and Albert Chin and Kwong, {D. L.}",

year = "2004",

month = oct,

day = "1",

doi = "10.1016/j.sse.2004.05.045",

language = "English",

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pages = "1987--1992",

journal = "Solid-State Electronics",

issn = "0038-1101",

publisher = "Elsevier Ltd",

number = "10-11 SPEC. ISS.",

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Zhu, S, Yu, HY, Chen, JD, Whang, SJ, Chen, JH, Shen, C, Zhu, C, Lee, SJ, Li, MF, Chan, DSH, Yoo, WJ, Du, A, Tung, CH, Singh, J, Chin, A & Kwong, DL 2004, 'Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode', Solid-State Electronics, vol. 48, no. 10-11 SPEC. ISS., pp. 1987-1992. https://doi.org/10.1016/j.sse.2004.05.045

TY - JOUR

T1 - Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode

AU - Zhu, Shiyang

AU - Yu, H. Y.

AU - Chen, J. D.

AU - Whang, S. J.

AU - Chen, J. H.

AU - Shen, Chen

AU - Zhu, Chunxiang

AU - Lee, S. J.

AU - Li, M. F.

AU - Chan, D. S.H.

AU - Yoo, W. J.

AU - Du, Anyan

AU - Tung, C. H.

AU - Singh, Jagar

AU - Chin, Albert

AU - Kwong, D. L.

PY - 2004/10/1

Y1 - 2004/10/1

N2 - Both P- and N-channel MOSFETs with Schottky barrier silicide source/drain (S/D), high-K gate dielectric and metal gate were successfully fabricated using a simplified low temperature process. The highest temperature after the high-K dielectric formation is 420°C. PMOSFETs with PtSi S/D show excellent electrical performance of an Ion/Ioff ∼ 10 7-108 and a subthreshold slope of 66 mV/dec, similar to those formed by a normal process with an optimized sidewall spacer. NMOSFETs with DySi2-x S/D have ∼3 orders of magnitude larger I off than that of PMOSFETs and show two slopes in the subthreshold region, resulting in the Ion/Ioff ∼ 105 at low drain voltage. It can be attributed to the relatively higher barrier height (Φn) of DySi2-x/n-Si than that of PtSi/p-Si (Φp) and the rougher DySi2-x film. Adding a thin intermediate Ge layer (∼1 nm) between Dy and Si can improve the film morphology significantly. As a result, the improved performance of N-MOSFET is observed.

AB - Both P- and N-channel MOSFETs with Schottky barrier silicide source/drain (S/D), high-K gate dielectric and metal gate were successfully fabricated using a simplified low temperature process. The highest temperature after the high-K dielectric formation is 420°C. PMOSFETs with PtSi S/D show excellent electrical performance of an Ion/Ioff ∼ 10 7-108 and a subthreshold slope of 66 mV/dec, similar to those formed by a normal process with an optimized sidewall spacer. NMOSFETs with DySi2-x S/D have ∼3 orders of magnitude larger I off than that of PMOSFETs and show two slopes in the subthreshold region, resulting in the Ion/Ioff ∼ 105 at low drain voltage. It can be attributed to the relatively higher barrier height (Φn) of DySi2-x/n-Si than that of PtSi/p-Si (Φp) and the rougher DySi2-x film. Adding a thin intermediate Ge layer (∼1 nm) between Dy and Si can improve the film morphology significantly. As a result, the improved performance of N-MOSFET is observed.

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U2 - 10.1016/j.sse.2004.05.045

DO - 10.1016/j.sse.2004.05.045

M3 - Article

AN - SCOPUS:3142674504

SN - 0038-1101

VL - 48

SP - 1987

EP - 1992

JO - Solid-State Electronics

JF - Solid-State Electronics

IS - 10-11 SPEC. ISS.

ER -

Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode

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