Low Temperature Cu-Cu Bonding Technology in Three-Dimensional Integration: An Extensive Review

Asisa Kumar Panigrahy, Kuan-Neng Chen*

*Corresponding author for this work

Research output: Contribution to journalReview articlepeer-review

65 Scopus citations


Arguably, the integrated circuit (IC) industry has received robust scientific and technological attention due to the ultra-small and extremely fast transistors since past four decades that consents to Moore's law. The introduction of new interconnect materials as well as innovative architectures has aided for large-scale miniaturization of devices, but their contributions were limited. Thus, the focus has shifted toward the development of new integration approaches that reduce the interconnect delays which has been achieved successfully by three-dimensional integrated circuit (3D IC). At this juncture, semiconductor industries utilize Cu-Cu bonding as a key technique for 3D IC integration. This review paper focuses on the key role of low temperature Cu-Cu bonding, renaissance of the low temperature bonding, and current research trends to achieve low temperature Cu-Cu bonding for 3D IC and heterogeneous integration applications.

Original languageEnglish
Article number010801
Pages (from-to)1-11
Number of pages11
JournalJournal of Electronic Packaging, Transactions of the ASME
Issue number1
StatePublished - 1 Mar 2018


  • 3D packaging
  • Bumping
  • Chip stacking


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