Abstract
This study explores a novel area-selective passivation bonding technology utilizing gold, a crucial facilitator for heterogeneous integration, which fulfills the urgent demand for high-performance computing (HPC). This mask-free patterning bonding technology allows for chip bonding at ambient temperatures under 120 °C within a short timeframe, successfully mitigating copper oxidation and post-chemical mechanical polishing (CMP) dishing issues without additional high-cost lithography. The technology, with its area-selective features, proves versatile for a variety of bonding structures, such as copper pillars, interconnect Cu-Cu, and Cu/SiO2 bonding, circumventing lithography issues and streamlining the traditional metal passivation bonding process. Our investigation confirms the superior quality and robustness of these area-selective films, together with the robust electrical performance of both interconnect Cu-Cu and Cu/SiO2 hybrid bonding devices.
Original language | English |
---|---|
Pages (from-to) | 1273-1276 |
Number of pages | 4 |
Journal | Ieee Electron Device Letters |
Volume | 45 |
Issue number | 7 |
DOIs | |
State | Published - 1 Jul 2024 |
Keywords
- 3D integration
- Cu bonding
- chiplet
- passivation structure