Low-spur technique for integer-N phase-locked loop

Te Wen Liao; Jun Ren Su; Chung-Chih Hung

doi:10.1109/MWSCAS.2012.6292078

Low-spur technique for integer-N phase-locked loop

Te Wen Liao^*, Jun Ren Su, Chung-Chih Hung

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

In this paper, we presents a low-spur phase locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator (VCO) in order to reduce the reference spur at the output of the PLL. A new random clock generator is presented to perform a random selection of phase frequency detector (PFD) control for charge pump at locked state. The proposed frequency synthesizer was fabricated in TSMC 0.18-μm CMOS process. The PLL has achieved the phase noise of -105 dBc/Hz at 1MHz offset frequency and reference spurs below -72dBc.

Original language	English
Title of host publication	2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
Pages	546-549
Number of pages	4
DOIs	https://doi.org/10.1109/MWSCAS.2012.6292078
State	Published - 2012
Event	2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012 - Boise, ID, United States Duration: 5 Aug 2012 → 8 Aug 2012

Publication series

Name	Midwest Symposium on Circuits and Systems
ISSN (Print)	1548-3746

Conference

Conference	2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
Country/Territory	United States
City	Boise, ID
Period	5/08/12 → 8/08/12

Keywords

PLL
Synthesizer
low spur

Access to Document

10.1109/MWSCAS.2012.6292078

Cite this

@inproceedings{78602700b1c7434f80f21dd8ce37da35,

title = "Low-spur technique for integer-N phase-locked loop",

abstract = "In this paper, we presents a low-spur phase locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator (VCO) in order to reduce the reference spur at the output of the PLL. A new random clock generator is presented to perform a random selection of phase frequency detector (PFD) control for charge pump at locked state. The proposed frequency synthesizer was fabricated in TSMC 0.18-μm CMOS process. The PLL has achieved the phase noise of -105 dBc/Hz at 1MHz offset frequency and reference spurs below -72dBc.",

keywords = "PLL, Synthesizer, low spur",

author = "Liao, {Te Wen} and Su, {Jun Ren} and Chung-Chih Hung",

year = "2012",

doi = "10.1109/MWSCAS.2012.6292078",

language = "English",

isbn = "9781467325264",

series = "Midwest Symposium on Circuits and Systems",

pages = "546--549",

booktitle = "2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012",

note = "2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012 ; Conference date: 05-08-2012 Through 08-08-2012",

}

Liao, TW, Su, JR & Hung, C-C 2012, Low-spur technique for integer-N phase-locked loop. in 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012., 6292078, Midwest Symposium on Circuits and Systems, pp. 546-549, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012, Boise, ID, United States, 5/08/12. https://doi.org/10.1109/MWSCAS.2012.6292078

TY - GEN

T1 - Low-spur technique for integer-N phase-locked loop

AU - Liao, Te Wen

AU - Su, Jun Ren

AU - Hung, Chung-Chih

PY - 2012

Y1 - 2012

N2 - In this paper, we presents a low-spur phase locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator (VCO) in order to reduce the reference spur at the output of the PLL. A new random clock generator is presented to perform a random selection of phase frequency detector (PFD) control for charge pump at locked state. The proposed frequency synthesizer was fabricated in TSMC 0.18-μm CMOS process. The PLL has achieved the phase noise of -105 dBc/Hz at 1MHz offset frequency and reference spurs below -72dBc.

AB - In this paper, we presents a low-spur phase locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator (VCO) in order to reduce the reference spur at the output of the PLL. A new random clock generator is presented to perform a random selection of phase frequency detector (PFD) control for charge pump at locked state. The proposed frequency synthesizer was fabricated in TSMC 0.18-μm CMOS process. The PLL has achieved the phase noise of -105 dBc/Hz at 1MHz offset frequency and reference spurs below -72dBc.

KW - PLL

KW - Synthesizer

KW - low spur

UR - http://www.scopus.com/inward/record.url?scp=84867295275&partnerID=8YFLogxK

U2 - 10.1109/MWSCAS.2012.6292078

DO - 10.1109/MWSCAS.2012.6292078

M3 - Conference contribution

AN - SCOPUS:84867295275

SN - 9781467325264

T3 - Midwest Symposium on Circuits and Systems

SP - 546

EP - 549

BT - 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012

T2 - 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012

Y2 - 5 August 2012 through 8 August 2012

ER -

Low-spur technique for integer-N phase-locked loop

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this