Low-power techniques for network security processors

Yi-Ping You; Chun Yen Tseng; Yu Hui Huang; Po Chiun Huang; Ting Ting Hwang; Sheng Yu Hsu

doi:10.1109/ASPDAC.2005.1466188

Low-power techniques for network security processors

Yi-Ping You^*, Chun Yen Tseng, Yu Hui Huang, Po Chiun Huang, Ting Ting Hwang, Sheng Yu Hsu

^*Corresponding author for this work

Institute of Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and dual threshold voltage assignments, for network security processors. The experiments show that the proposed methods and designs provide the opportunity for network security processors to achieve the goals of both high performance and low power.

Original language	English
Title of host publication	Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Pages	355-360
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2005.1466188
State	Published - 1 Dec 2005
Event	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China Duration: 18 Jan 2005 → 21 Jan 2005

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	1

Conference

Conference	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Country/Territory	China
City	Shanghai
Period	18/01/05 → 21/01/05

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10.1109/ASPDAC.2005.1466188

Cite this

You, Y.-P., Tseng, C. Y., Huang, Y. H., Huang, P. C., Hwang, T. T., & Hsu, S. Y. (2005). Low-power techniques for network security processors. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 (pp. 355-360). Article 1466188 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1). https://doi.org/10.1109/ASPDAC.2005.1466188

@inproceedings{f4de51349c5f44b1b1bcf919f8ce6cc1,

title = "Low-power techniques for network security processors",

abstract = "In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and dual threshold voltage assignments, for network security processors. The experiments show that the proposed methods and designs provide the opportunity for network security processors to achieve the goals of both high performance and low power.",

author = "Yi-Ping You and Tseng, {Chun Yen} and Huang, {Yu Hui} and Huang, {Po Chiun} and Hwang, {Ting Ting} and Hsu, {Sheng Yu}",

year = "2005",

month = dec,

day = "1",

doi = "10.1109/ASPDAC.2005.1466188",

language = "English",

isbn = "0780387368",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

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booktitle = "Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005",

note = "2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 ; Conference date: 18-01-2005 Through 21-01-2005",

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You, Y-P, Tseng, CY, Huang, YH, Huang, PC, Hwang, TT & Hsu, SY 2005, Low-power techniques for network security processors. in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005., 1466188, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 1, pp. 355-360, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, China, 18/01/05. https://doi.org/10.1109/ASPDAC.2005.1466188

Low-power techniques for network security processors. / You, Yi-Ping; Tseng, Chun Yen; Huang, Yu Hui et al.
Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. 2005. p. 355-360 1466188 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and dual threshold voltage assignments, for network security processors. The experiments show that the proposed methods and designs provide the opportunity for network security processors to achieve the goals of both high performance and low power.

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Low-power techniques for network security processors

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