Low-power self-timed circuit design technique

Shyh-Jye Jou; I. Yao Chung

doi:10.1049/el:19970110

Low-power self-timed circuit design technique

Shyh-Jye Jou^*, I. Yao Chung

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

An implementation of self-timed circuits whose hardware and control signals are significantly reduced is proposed. A globally asynchronous locally synchronous design using the proposed self-timed circuits is also demonstrated. A design example shows that in this implementation less power is consumed with only a small circuit overhead.

Original language	English
Pages (from-to)	110-111
Number of pages	2
Journal	Electronics Letters
Volume	33
Issue number	2
DOIs	https://doi.org/10.1049/el:19970110
State	Published - 16 Jan 1997

Keywords

Digital circuits
Timing

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10.1049/el:19970110

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title = "Low-power self-timed circuit design technique",

abstract = "An implementation of self-timed circuits whose hardware and control signals are significantly reduced is proposed. A globally asynchronous locally synchronous design using the proposed self-timed circuits is also demonstrated. A design example shows that in this implementation less power is consumed with only a small circuit overhead.",

keywords = "Digital circuits, Timing",

author = "Shyh-Jye Jou and Chung, {I. Yao}",

year = "1997",

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KW - Timing

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Low-power self-timed circuit design technique

Abstract

Keywords

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