Abstract
An implementation of self-timed circuits whose hardware and control signals are significantly reduced is proposed. A globally asynchronous locally synchronous design using the proposed self-timed circuits is also demonstrated. A design example shows that in this implementation less power is consumed with only a small circuit overhead.
Original language | English |
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Pages (from-to) | 110-111 |
Number of pages | 2 |
Journal | Electronics Letters |
Volume | 33 |
Issue number | 2 |
DOIs | |
State | Published - 16 Jan 1997 |
Keywords
- Digital circuits
- Timing