Low-power self-timed circuit design technique

Shyh-Jye Jou*, I. Yao Chung

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


An implementation of self-timed circuits whose hardware and control signals are significantly reduced is proposed. A globally asynchronous locally synchronous design using the proposed self-timed circuits is also demonstrated. A design example shows that in this implementation less power is consumed with only a small circuit overhead.

Original languageEnglish
Pages (from-to)110-111
Number of pages2
JournalElectronics Letters
Issue number2
StatePublished - 16 Jan 1997


  • Digital circuits
  • Timing


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