Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash

Shantanu Rajwade; Wing Kei Yu; Sarah Xu; Tuo-Hung Hou; G. Edward Suh; Edwin Kan

doi:10.1109/SOCC.2010.5784679

Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash

Shantanu Rajwade^*, Wing Kei Yu, Sarah Xu, Tuo-Hung Hou, G. Edward Suh, Edwin Kan

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

This paper presents a new nonvolatile SRAM design that incorporates low-voltage nanocrystal PMOS Flash transistors. The design enables global store, restore and erase operations with negligible penalty on regular SRAM operation. Store/erase operations also do not consume much power even considering charge pump circuits. Circuit simulations based on experimental I-V characteristics demonstrate that 10 s store/erase operation at 6 Vis sufficient for correct restoration of the stored bit even under reasonable process variation.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2010
Pages	461-466
Number of pages	6
DOIs	https://doi.org/10.1109/SOCC.2010.5784679
State	Published - 1 Dec 2010
Event	23rd IEEE International SOC Conference, SOCC 2010 - Las Vegas, NV, United States Duration: 27 Sep 2010 → 29 Sep 2010

Publication series

Name	Proceedings - IEEE International SOC Conference, SOCC 2010

Conference

Conference	23rd IEEE International SOC Conference, SOCC 2010
Country/Territory	United States
City	Las Vegas, NV
Period	27/09/10 → 29/09/10

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10.1109/SOCC.2010.5784679

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@inproceedings{7de4960ce52d4296b4952d977df98748,

title = "Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash",

abstract = "This paper presents a new nonvolatile SRAM design that incorporates low-voltage nanocrystal PMOS Flash transistors. The design enables global store, restore and erase operations with negligible penalty on regular SRAM operation. Store/erase operations also do not consume much power even considering charge pump circuits. Circuit simulations based on experimental I-V characteristics demonstrate that 10 s store/erase operation at 6 Vis sufficient for correct restoration of the stored bit even under reasonable process variation.",

author = "Shantanu Rajwade and Yu, {Wing Kei} and Sarah Xu and Tuo-Hung Hou and Suh, {G. Edward} and Edwin Kan",

year = "2010",

month = dec,

day = "1",

doi = "10.1109/SOCC.2010.5784679",

language = "English",

isbn = "9781424466832",

series = "Proceedings - IEEE International SOC Conference, SOCC 2010",

pages = "461--466",

booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2010",

note = "23rd IEEE International SOC Conference, SOCC 2010 ; Conference date: 27-09-2010 Through 29-09-2010",

}

Rajwade, S, Yu, WK, Xu, S, Hou, T-H, Suh, GE & Kan, E 2010, Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash. in Proceedings - IEEE International SOC Conference, SOCC 2010., 5784679, Proceedings - IEEE International SOC Conference, SOCC 2010, pp. 461-466, 23rd IEEE International SOC Conference, SOCC 2010, Las Vegas, NV, United States, 27/09/10. https://doi.org/10.1109/SOCC.2010.5784679

Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash. / Rajwade, Shantanu; Yu, Wing Kei; Xu, Sarah et al.
Proceedings - IEEE International SOC Conference, SOCC 2010. 2010. p. 461-466 5784679 (Proceedings - IEEE International SOC Conference, SOCC 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash

AU - Rajwade, Shantanu

AU - Yu, Wing Kei

AU - Xu, Sarah

AU - Hou, Tuo-Hung

AU - Suh, G. Edward

AU - Kan, Edwin

PY - 2010/12/1

Y1 - 2010/12/1

N2 - This paper presents a new nonvolatile SRAM design that incorporates low-voltage nanocrystal PMOS Flash transistors. The design enables global store, restore and erase operations with negligible penalty on regular SRAM operation. Store/erase operations also do not consume much power even considering charge pump circuits. Circuit simulations based on experimental I-V characteristics demonstrate that 10 s store/erase operation at 6 Vis sufficient for correct restoration of the stored bit even under reasonable process variation.

AB - This paper presents a new nonvolatile SRAM design that incorporates low-voltage nanocrystal PMOS Flash transistors. The design enables global store, restore and erase operations with negligible penalty on regular SRAM operation. Store/erase operations also do not consume much power even considering charge pump circuits. Circuit simulations based on experimental I-V characteristics demonstrate that 10 s store/erase operation at 6 Vis sufficient for correct restoration of the stored bit even under reasonable process variation.

UR - http://www.scopus.com/inward/record.url?scp=79960736605&partnerID=8YFLogxK

U2 - 10.1109/SOCC.2010.5784679

DO - 10.1109/SOCC.2010.5784679

M3 - Conference contribution

AN - SCOPUS:79960736605

SN - 9781424466832

T3 - Proceedings - IEEE International SOC Conference, SOCC 2010

SP - 461

EP - 466

BT - Proceedings - IEEE International SOC Conference, SOCC 2010

T2 - 23rd IEEE International SOC Conference, SOCC 2010

Y2 - 27 September 2010 through 29 September 2010

ER -

Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash

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