Low-power multirate IF digital frequency down converter

Shyh-Jye Jou; Shou Yang Wu; Chorng Kuang Wang

doi:10.1109/VTSA.1999.786042

Low-power multirate IF digital frequency down converter

Shyh-Jye Jou^*, Shou Yang Wu, Chorng Kuang Wang

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

Abstract

The architecture design of the proposed IF digital frequency down converter (DFDC) is the combination of 4-IF oversampling and multistage interpolated finite impulse response filter design techniques based on multirate algorithm. It can have very low-power dissipation owing to its reduction in hardware complexity and operational frequency. Design application for IS-95 CDMA with IF frequency at 4.9152 MHz shows that the DFDC only consumes 0.6mW when operates at 2 V.

Original language	English
Pages (from-to)	231-234
Number of pages	4
Journal	International Symposium on VLSI Technology, Systems, and Applications, Proceedings
DOIs	https://doi.org/10.1109/VTSA.1999.786042
State	Published - 1 Jan 1999
Event	Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan Duration: 7 Jun 1999 → 10 Jun 1999

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abstract = "The architecture design of the proposed IF digital frequency down converter (DFDC) is the combination of 4-IF oversampling and multistage interpolated finite impulse response filter design techniques based on multirate algorithm. It can have very low-power dissipation owing to its reduction in hardware complexity and operational frequency. Design application for IS-95 CDMA with IF frequency at 4.9152 MHz shows that the DFDC only consumes 0.6mW when operates at 2 V.",

author = "Shyh-Jye Jou and Wu, {Shou Yang} and Wang, {Chorng Kuang}",

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AU - Wu, Shou Yang

AU - Wang, Chorng Kuang

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N2 - The architecture design of the proposed IF digital frequency down converter (DFDC) is the combination of 4-IF oversampling and multistage interpolated finite impulse response filter design techniques based on multirate algorithm. It can have very low-power dissipation owing to its reduction in hardware complexity and operational frequency. Design application for IS-95 CDMA with IF frequency at 4.9152 MHz shows that the DFDC only consumes 0.6mW when operates at 2 V.

AB - The architecture design of the proposed IF digital frequency down converter (DFDC) is the combination of 4-IF oversampling and multistage interpolated finite impulse response filter design techniques based on multirate algorithm. It can have very low-power dissipation owing to its reduction in hardware complexity and operational frequency. Design application for IS-95 CDMA with IF frequency at 4.9152 MHz shows that the DFDC only consumes 0.6mW when operates at 2 V.

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DO - 10.1109/VTSA.1999.786042

M3 - Conference article

AN - SCOPUS:0032599160

SN - 1524-766X

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EP - 234

JO - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

JF - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

T2 - Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications

Y2 - 7 June 1999 through 10 June 1999

ER -

Low-power multirate IF digital frequency down converter

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