Low-power multiplierless FIR filter synthesizer based on CSD code

Maw Ching Liu; Chien Lung Chen; Ding Yu Shin; Chin Hung Lin; Shyh-Jye Jou

doi:10.1109/ISCAS.2001.922325

Low-power multiplierless FIR filter synthesizer based on CSD code

Maw Ching Liu, Chien Lung Chen, Ding Yu Shin, Chin Hung Lin, Shyh-Jye Jou

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

An architecture synthesizer for FIR filter based on CSD code is presented. Traditional filter synthesis tool only generates one set of coefficient that fits the filter specifications. However, in the time and frequency optimization of the filter coefficients, our synthesizer can obtain as many sets of coefficient as possible. The coefficient set that leads to minimum hardware complexity will be selected. Four structures that range is from the fastest speed to the least area can be selected by user. Finally, a synthesizable Verilog code will be automatically generated. A design example that the FIR has 35 taps with 8-bit coefficients shows that the overall hardware reduction by using our synthesizer is 58% as compared to the original design.

Original language	English
Title of host publication	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages	666-669
Number of pages	4
Volume	626
DOIs	https://doi.org/10.1109/ISCAS.2001.922325
State	Published - 1 Dec 2001
Event	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia Duration: 6 May 2001 → 9 May 2001

Publication series

Name	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume	4

Conference

Conference	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Country/Territory	Australia
City	Sydney, NSW
Period	6/05/01 → 9/05/01

Access to Document

10.1109/ISCAS.2001.922325

Cite this

Liu, M. C., Chen, C. L., Shin, D. Y., Lin, C. H., & Jou, S.-J. (2001). Low-power multiplierless FIR filter synthesizer based on CSD code. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (Vol. 626, pp. 666-669). Article 922325 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 4). https://doi.org/10.1109/ISCAS.2001.922325

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title = "Low-power multiplierless FIR filter synthesizer based on CSD code",

abstract = "An architecture synthesizer for FIR filter based on CSD code is presented. Traditional filter synthesis tool only generates one set of coefficient that fits the filter specifications. However, in the time and frequency optimization of the filter coefficients, our synthesizer can obtain as many sets of coefficient as possible. The coefficient set that leads to minimum hardware complexity will be selected. Four structures that range is from the fastest speed to the least area can be selected by user. Finally, a synthesizable Verilog code will be automatically generated. A design example that the FIR has 35 taps with 8-bit coefficients shows that the overall hardware reduction by using our synthesizer is 58% as compared to the original design.",

author = "Liu, {Maw Ching} and Chen, {Chien Lung} and Shin, {Ding Yu} and Lin, {Chin Hung} and Shyh-Jye Jou",

year = "2001",

month = dec,

day = "1",

doi = "10.1109/ISCAS.2001.922325",

language = "English",

isbn = "0780366859",

volume = "626",

series = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",

pages = "666--669",

booktitle = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",

note = "2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 ; Conference date: 06-05-2001 Through 09-05-2001",

}

Liu, MC, Chen, CL, Shin, DY, Lin, CH & Jou, S-J 2001, Low-power multiplierless FIR filter synthesizer based on CSD code. in ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. vol. 626, 922325, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, vol. 4, pp. 666-669, 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, NSW, Australia, 6/05/01. https://doi.org/10.1109/ISCAS.2001.922325

Low-power multiplierless FIR filter synthesizer based on CSD code. / Liu, Maw Ching; Chen, Chien Lung; Shin, Ding Yu et al.
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. Vol. 626 2001. p. 666-669 922325 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 4).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - An architecture synthesizer for FIR filter based on CSD code is presented. Traditional filter synthesis tool only generates one set of coefficient that fits the filter specifications. However, in the time and frequency optimization of the filter coefficients, our synthesizer can obtain as many sets of coefficient as possible. The coefficient set that leads to minimum hardware complexity will be selected. Four structures that range is from the fastest speed to the least area can be selected by user. Finally, a synthesizable Verilog code will be automatically generated. A design example that the FIR has 35 taps with 8-bit coefficients shows that the overall hardware reduction by using our synthesizer is 58% as compared to the original design.

AB - An architecture synthesizer for FIR filter based on CSD code is presented. Traditional filter synthesis tool only generates one set of coefficient that fits the filter specifications. However, in the time and frequency optimization of the filter coefficients, our synthesizer can obtain as many sets of coefficient as possible. The coefficient set that leads to minimum hardware complexity will be selected. Four structures that range is from the fastest speed to the least area can be selected by user. Finally, a synthesizable Verilog code will be automatically generated. A design example that the FIR has 35 taps with 8-bit coefficients shows that the overall hardware reduction by using our synthesizer is 58% as compared to the original design.

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Liu MC, Chen CL, Shin DY, Lin CH, Jou SJ. Low-power multiplierless FIR filter synthesizer based on CSD code. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. Vol. 626. 2001. p. 666-669. 922325. (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings). doi: 10.1109/ISCAS.2001.922325

Low-power multiplierless FIR filter synthesizer based on CSD code

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