Low-power instruction cache architecture using pre-tag checking

Shi You Cheng; Juinn-Dar Huang

doi:10.1109/VDAT.2007.373216

Low-power instruction cache architecture using pre-tag checking

Shi You Cheng^*, Juinn-Dar Huang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, we propose a low-power instruction cache architecture utilizing three techniques two-phased cache, sequential access indicator for tag-memory access skipping, and a new proposed technique namedpre-tag checking. By these techniques, significant portion of tag-memory and data-memory accesses can be eliminated to reduce the power consumption. The experimental results show that the proposed instruction cache architecture can reduce about 54% power consumption compared to the conventional one for an 8KB two-way set associative cache.

Original language	English
Title of host publication	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOIs	https://doi.org/10.1109/VDAT.2007.373216
State	Published - 28 Sep 2007
Event	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan Duration: 25 Apr 2007 → 27 Apr 2007

Publication series

Name	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Conference

Conference	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
Country/Territory	Taiwan
City	Hsinchu
Period	25/04/07 → 27/04/07

Access to Document

10.1109/VDAT.2007.373216

Cite this

Cheng, S. Y., & Huang, J.-D. (2007). Low-power instruction cache architecture using pre-tag checking. In 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers Article 4239408 (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2007.373216

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title = "Low-power instruction cache architecture using pre-tag checking",

abstract = "In this paper, we propose a low-power instruction cache architecture utilizing three techniques two-phased cache, sequential access indicator for tag-memory access skipping, and a new proposed technique namedpre-tag checking. By these techniques, significant portion of tag-memory and data-memory accesses can be eliminated to reduce the power consumption. The experimental results show that the proposed instruction cache architecture can reduce about 54% power consumption compared to the conventional one for an 8KB two-way set associative cache.",

author = "Cheng, {Shi You} and Juinn-Dar Huang",

year = "2007",

month = sep,

day = "28",

doi = "10.1109/VDAT.2007.373216",

language = "English",

isbn = "1424405831",

series = "2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers",

booktitle = "2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers",

note = "2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 ; Conference date: 25-04-2007 Through 27-04-2007",

}

Cheng, SY & Huang, J-D 2007, Low-power instruction cache architecture using pre-tag checking. in 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers., 4239408, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007, Hsinchu, Taiwan, 25/04/07. https://doi.org/10.1109/VDAT.2007.373216

Low-power instruction cache architecture using pre-tag checking. / Cheng, Shi You; Huang, Juinn-Dar.
2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 2007. 4239408 (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, we propose a low-power instruction cache architecture utilizing three techniques two-phased cache, sequential access indicator for tag-memory access skipping, and a new proposed technique namedpre-tag checking. By these techniques, significant portion of tag-memory and data-memory accesses can be eliminated to reduce the power consumption. The experimental results show that the proposed instruction cache architecture can reduce about 54% power consumption compared to the conventional one for an 8KB two-way set associative cache.

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Low-power instruction cache architecture using pre-tag checking

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