Low-power globally asynchronous locally synchronous design using self-timed circuit technology

Shyh-Jye Jou; I. Yao Chuang

doi:10.1109/ISCAS.1997.621497

Low-power globally asynchronous locally synchronous design using self-timed circuit technology

Shyh-Jye Jou^*, I. Yao Chuang

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

3 Scopus citations

Abstract

In this paper, an efficient implementation of self-timed circuits whose hardware and control signals are significantly reduced is first proposed. By applying Globally Asynchronous Locally Synchronous (GALS) design techniques, the hardware overhead is further reduced. GALS and synchronous version of 8-bit fully pipelined array multipliers are implemented for comparisons. The results show that GALS version has smaller peak current, less power consumption under variable workload with small hardware overhead as compared to synchronous version.

Original language	English
Article number	5745106
Pages (from-to)	1808-1811
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
DOIs	https://doi.org/10.1109/ISCAS.1997.621497
State	Published - 1 Jan 1997
Event	Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong Duration: 9 Jun 1997 → 12 Jun 1997

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10.1109/ISCAS.1997.621497

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abstract = "In this paper, an efficient implementation of self-timed circuits whose hardware and control signals are significantly reduced is first proposed. By applying Globally Asynchronous Locally Synchronous (GALS) design techniques, the hardware overhead is further reduced. GALS and synchronous version of 8-bit fully pipelined array multipliers are implemented for comparisons. The results show that GALS version has smaller peak current, less power consumption under variable workload with small hardware overhead as compared to synchronous version.",

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AU - Chuang, I. Yao

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N2 - In this paper, an efficient implementation of self-timed circuits whose hardware and control signals are significantly reduced is first proposed. By applying Globally Asynchronous Locally Synchronous (GALS) design techniques, the hardware overhead is further reduced. GALS and synchronous version of 8-bit fully pipelined array multipliers are implemented for comparisons. The results show that GALS version has smaller peak current, less power consumption under variable workload with small hardware overhead as compared to synchronous version.

AB - In this paper, an efficient implementation of self-timed circuits whose hardware and control signals are significantly reduced is first proposed. By applying Globally Asynchronous Locally Synchronous (GALS) design techniques, the hardware overhead is further reduced. GALS and synchronous version of 8-bit fully pipelined array multipliers are implemented for comparisons. The results show that GALS version has smaller peak current, less power consumption under variable workload with small hardware overhead as compared to synchronous version.

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M3 - Conference article

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JO - Proceedings - IEEE International Symposium on Circuits and Systems

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Y2 - 9 June 1997 through 12 June 1997

ER -

Low-power globally asynchronous locally synchronous design using self-timed circuit technology

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