TY - GEN
T1 - Low-power gated clock tree optimization for three-dimensional integrated circuits
AU - Chen, Yu Chuan
AU - Hsu, Chih Cheng
AU - Lin, Po-Hung
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/5/28
Y1 - 2015/5/28
N2 - Applying clock gating in three dimensional integrated circuits (3D ICs) is essential for reducing power consumption and improving circuit reliability. However, the previous works only present algorithms for 3D clock tree synthesis. None of them address gated clock tree in 3D ICs for dynamic power reduction. In this paper, we propose the first problem formulation in the literature for 3D gated clock network optimization. We consider both flip-flop switching activities and the timing constraint of enable signal paths at clock gating cells when constructing topological gated clock trees. Based on the topological gated clock trees, a zero-skew 3D clock routing tree is then generated. Experimental results show that, compared with conventional 3D clock tree synthesis, the proposed 3D gated clock tree synthesis can achieve much less power consumption with similar number of TSVs and clock tree wirelength.
AB - Applying clock gating in three dimensional integrated circuits (3D ICs) is essential for reducing power consumption and improving circuit reliability. However, the previous works only present algorithms for 3D clock tree synthesis. None of them address gated clock tree in 3D ICs for dynamic power reduction. In this paper, we propose the first problem formulation in the literature for 3D gated clock network optimization. We consider both flip-flop switching activities and the timing constraint of enable signal paths at clock gating cells when constructing topological gated clock trees. Based on the topological gated clock trees, a zero-skew 3D clock routing tree is then generated. Experimental results show that, compared with conventional 3D clock tree synthesis, the proposed 3D gated clock tree synthesis can achieve much less power consumption with similar number of TSVs and clock tree wirelength.
UR - http://www.scopus.com/inward/record.url?scp=84936972744&partnerID=8YFLogxK
U2 - 10.1109/VLSI-DAT.2015.7114530
DO - 10.1109/VLSI-DAT.2015.7114530
M3 - Conference contribution
AN - SCOPUS:84936972744
T3 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
BT - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Y2 - 27 April 2015 through 29 April 2015
ER -