@inproceedings{c50ede7128054aa4a5d7153b9d7073df,
title = "Low-power gated clock tree optimization for three-dimensional integrated circuits",
abstract = "Applying clock gating in three dimensional integrated circuits (3D ICs) is essential for reducing power consumption and improving circuit reliability. However, the previous works only present algorithms for 3D clock tree synthesis. None of them address gated clock tree in 3D ICs for dynamic power reduction. In this paper, we propose the first problem formulation in the literature for 3D gated clock network optimization. We consider both flip-flop switching activities and the timing constraint of enable signal paths at clock gating cells when constructing topological gated clock trees. Based on the topological gated clock trees, a zero-skew 3D clock routing tree is then generated. Experimental results show that, compared with conventional 3D clock tree synthesis, the proposed 3D gated clock tree synthesis can achieve much less power consumption with similar number of TSVs and clock tree wirelength.",
author = "Chen, {Yu Chuan} and Hsu, {Chih Cheng} and Po-Hung Lin",
year = "2015",
month = may,
day = "28",
doi = "10.1109/VLSI-DAT.2015.7114530",
language = "English",
series = "2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015",
address = "United States",
note = "2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 ; Conference date: 27-04-2015 Through 29-04-2015",
}