Low power encoding schemes for run-time on-chip bus

Po-Tsang Huang; Wei Hwang

doi:10.1109/APCCAS.2004.1413057

Low power encoding schemes for run-time on-chip bus

Po-Tsang Huang^*, Wei Hwang

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Contribution to conference › Paper › peer-review

3 Scopus citations

Abstract

The coupling effect dominates the power consumption during the run-time in on-chip buses. In this paper we present two low power bus encoding design schemes, one-half encoding and two phase encoding, for reducing the coupling effect in SoC interconnects. Minimizing the power consumption is an important issue for on-chip bus in SoC design in deep submicron technology. There are various approaches to reduce the coupling effect, and we focus on the encoding scheme of reduction of transition activities. Applied data streams contain random data, JPFG, MPEG, MP3 and PDF. Our simulation results indicate that our proposed schemes can save the power 36% for one-half encoding scheme and 31% for two phase encoding scheme by using HSPICE of TSMC 100nm technology.

Original language	English
Pages	1025-1028
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2004.1413057
State	Published - Dec 2004
Event	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan Duration: 6 Dec 2004 → 9 Dec 2004

Conference

Conference	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
Country/Territory	Taiwan
City	Tainan
Period	6/12/04 → 9/12/04

Access to Document

10.1109/APCCAS.2004.1413057

Cite this

@conference{946a6ceb41434e57ad9d84223aa60d14,

title = "Low power encoding schemes for run-time on-chip bus",

abstract = "The coupling effect dominates the power consumption during the run-time in on-chip buses. In this paper we present two low power bus encoding design schemes, one-half encoding and two phase encoding, for reducing the coupling effect in SoC interconnects. Minimizing the power consumption is an important issue for on-chip bus in SoC design in deep submicron technology. There are various approaches to reduce the coupling effect, and we focus on the encoding scheme of reduction of transition activities. Applied data streams contain random data, JPFG, MPEG, MP3 and PDF. Our simulation results indicate that our proposed schemes can save the power 36% for one-half encoding scheme and 31% for two phase encoding scheme by using HSPICE of TSMC 100nm technology.",

author = "Po-Tsang Huang and Wei Hwang",

year = "2004",

month = dec,

doi = "10.1109/APCCAS.2004.1413057",

language = "English",

pages = "1025--1028",

note = "2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology ; Conference date: 06-12-2004 Through 09-12-2004",

}

TY - CONF

T1 - Low power encoding schemes for run-time on-chip bus

AU - Huang, Po-Tsang

AU - Hwang, Wei

PY - 2004/12

Y1 - 2004/12

N2 - The coupling effect dominates the power consumption during the run-time in on-chip buses. In this paper we present two low power bus encoding design schemes, one-half encoding and two phase encoding, for reducing the coupling effect in SoC interconnects. Minimizing the power consumption is an important issue for on-chip bus in SoC design in deep submicron technology. There are various approaches to reduce the coupling effect, and we focus on the encoding scheme of reduction of transition activities. Applied data streams contain random data, JPFG, MPEG, MP3 and PDF. Our simulation results indicate that our proposed schemes can save the power 36% for one-half encoding scheme and 31% for two phase encoding scheme by using HSPICE of TSMC 100nm technology.

AB - The coupling effect dominates the power consumption during the run-time in on-chip buses. In this paper we present two low power bus encoding design schemes, one-half encoding and two phase encoding, for reducing the coupling effect in SoC interconnects. Minimizing the power consumption is an important issue for on-chip bus in SoC design in deep submicron technology. There are various approaches to reduce the coupling effect, and we focus on the encoding scheme of reduction of transition activities. Applied data streams contain random data, JPFG, MPEG, MP3 and PDF. Our simulation results indicate that our proposed schemes can save the power 36% for one-half encoding scheme and 31% for two phase encoding scheme by using HSPICE of TSMC 100nm technology.

UR - http://www.scopus.com/inward/record.url?scp=21644485957&partnerID=8YFLogxK

U2 - 10.1109/APCCAS.2004.1413057

DO - 10.1109/APCCAS.2004.1413057

M3 - Paper

AN - SCOPUS:21644485957

SP - 1025

EP - 1028

T2 - 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology

Y2 - 6 December 2004 through 9 December 2004

ER -

Low power encoding schemes for run-time on-chip bus

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this