Low power correlator of DSP core for communication system

Ya Lan Tsao*, Jun Xian Teng, Maw Ching Lin, Shyh-Jye Jou

*Corresponding author for this work

    Research output: Contribution to conferencePaperpeer-review

    Abstract

    Correlator is the most demanded block in communication systems. In this paper, low power correlator block is implemented into an embedded DSP core as a special block. This special block of correlator can employ data bus bandwidth of DSP efficiently. The design results show that it use only 3235 gate counts and can reduce the correlation operations from 20 instructions (without correlator) to only 4 instructions.

    Original languageEnglish
    Pages217-220
    Number of pages4
    DOIs
    StatePublished - Dec 2004
    Event2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
    Duration: 6 Dec 20049 Dec 2004

    Conference

    Conference2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
    Country/TerritoryTaiwan
    CityTainan
    Period6/12/049/12/04

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