Low power and power aware design for DVB-T/H baseband inner receiver

Chi Yao Tseng*, Ting Chen Wei, Wei Chang Liu, Shyh-Jye Jou

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Scopus citations

    Abstract

    From hardware point of view, system and RTL low power and power aware design techniques are applied to the DVB-T/H baseband inner receiver. In RTL design, we use pre-computation, differential encoding, hardware sharing, time-multiplexing RAV of memory, low power arithmetic architecture so that each block can reduce power from 3% to 26%. In system level, the proposed DPM (Dynamic Power Manager) is a power control unit for our system. When the system enters the offset tracking mode, the DPM controls the power states of system blocks between the GI (Guard Interval) period and symbol period. The power reduction ratio ranges from 3%-20% (it depends on the GI mode). Moreover, a predicted phase scheme is proposed to provide the initial phase offset for the start of symbol period during offset tracking mode. The overall reduction for synchronization loop is about 50% in both hardware area and power.

    Original languageEnglish
    Title of host publication2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
    DOIs
    StatePublished - 28 Sep 2007
    Event2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan
    Duration: 25 Apr 200727 Apr 2007

    Publication series

    Name2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

    Conference

    Conference2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
    Country/TerritoryTaiwan
    CityHsinchu
    Period25/04/0727/04/07

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