Low-Power and Low-Voltage VLSI Circuit Design Techniques for Biomedical Applications

Chung Chih Hung*, Shih Hsing Wang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

1 Scopus citations

Abstract

Since wearable devices, sensor devices, or implanted devices are powered by batteries, they need to maintain long working time, especially implantable devices, because the battery needs to be replaced by surgery. This chapter introduces how to implement low-power, low-voltage VLSI circuit design. In addition to realizing more transistors in the same area to comply with Moore’s Law, advances in semiconductor technology have also brought many benefits, such as smaller areas, faster speed, more functions, and lower power consumption. From the perspective of technological evolution, there are many compromises in consideration of transistor characteristics. To produce good transistor characteristics, designers must weigh these transistor characteristics to achieve the best design performance or operating point. However, these advanced process nodes have also brought some problems, such as various leakage currents, and battery-powered devices cannot tolerate the waste of electricity. Therefore, we will discuss how to achieve low voltage and low power consumption in digital circuit design, including possible solutions and recommendations, and the trade-offs of reducing dynamic power, static power, and leakage current. Next, we will present the problems faced by low-voltage analog circuit design, and then discuss traditional design methods and gm/ID design methods. Finally, we will discuss some considerations for the design and implementation of nano-analog circuits.

Original languageEnglish
Title of host publicationAnalog Circuits and Signal Processing
PublisherSpringer
Pages23-54
Number of pages32
DOIs
StatePublished - 2022

Publication series

NameAnalog Circuits and Signal Processing
ISSN (Print)1872-082X
ISSN (Electronic)2197-1854

Keywords

  • Bias technology
  • Clock gating
  • Dynamic power
  • g/I design method
  • high-K dielectric
  • Multiple power-supply voltages
  • Near-threshold calculation (NTC)
  • OTA
  • Parallelism
  • PN junction reverse bias current (I)
  • Power gating
  • Signal integrity
  • Static power
  • Subthreshold leakage (I)
  • Tunneling into and through gate oxide (I)
  • Voltage scaling

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