Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology

Federico A. Altolaguirre, Ming-Dou Ker

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    3 Scopus citations

    Fingerprint

    Dive into the research topics of 'Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology'. Together they form a unique fingerprint.

    Engineering & Materials Science