Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology

Federico A. Altolaguirre; Ming-Dou Ker

doi:10.1109/ISCAS.2013.6572420

Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology

Federico A. Altolaguirre, Ming-Dou Ker

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A new power-rail ESD clamp circuit is proposed and verified with consideration of the gate leakage issue in 65-nm CMOS technology. The proposed circuit can reduce the total leakage current of the traditional power-rail ESD clamp circuit in two orders of magnitude. Moreover, the proposed circuit reduces the required silicon area by boosting the capacitor with a current mirror. The measured leakage current of the proposed power-rail ESD clamp circuit is 220nA (V_DD = 1V, T=25°C), much lower than the 20.55μA of the traditional design. In addition, the required area for the proposed design is 50μm × 30μm, which is a 40% reduction in silicon area to the traditional one, that can sustain the HBM (MM) ESD stress of 3.5kV (250V).

Original language	English
Title of host publication	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Pages	2638-2641
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2013.6572420
State	Published - 2013
Event	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China Duration: 19 May 2013 → 23 May 2013

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Country/Territory	China
City	Beijing
Period	19/05/13 → 23/05/13

Access to Document

10.1109/ISCAS.2013.6572420

Cite this

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title = "Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology",

abstract = "A new power-rail ESD clamp circuit is proposed and verified with consideration of the gate leakage issue in 65-nm CMOS technology. The proposed circuit can reduce the total leakage current of the traditional power-rail ESD clamp circuit in two orders of magnitude. Moreover, the proposed circuit reduces the required silicon area by boosting the capacitor with a current mirror. The measured leakage current of the proposed power-rail ESD clamp circuit is 220nA (VDD = 1V, T=25°C), much lower than the 20.55μA of the traditional design. In addition, the required area for the proposed design is 50μm × 30μm, which is a 40% reduction in silicon area to the traditional one, that can sustain the HBM (MM) ESD stress of 3.5kV (250V).",

author = "Altolaguirre, {Federico A.} and Ming-Dou Ker",

year = "2013",

doi = "10.1109/ISCAS.2013.6572420",

language = "English",

isbn = "9781467357609",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "2638--2641",

booktitle = "2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013",

note = "2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 ; Conference date: 19-05-2013 Through 23-05-2013",

}

Altolaguirre, FA & Ker, M-D 2013, Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology. in 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013., 6572420, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 2638-2641, 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013, Beijing, China, 19/05/13. https://doi.org/10.1109/ISCAS.2013.6572420

Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology. / Altolaguirre, Federico A.; Ker, Ming-Dou.
2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013. 2013. p. 2638-2641 6572420 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology

AU - Altolaguirre, Federico A.

AU - Ker, Ming-Dou

PY - 2013

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N2 - A new power-rail ESD clamp circuit is proposed and verified with consideration of the gate leakage issue in 65-nm CMOS technology. The proposed circuit can reduce the total leakage current of the traditional power-rail ESD clamp circuit in two orders of magnitude. Moreover, the proposed circuit reduces the required silicon area by boosting the capacitor with a current mirror. The measured leakage current of the proposed power-rail ESD clamp circuit is 220nA (VDD = 1V, T=25°C), much lower than the 20.55μA of the traditional design. In addition, the required area for the proposed design is 50μm × 30μm, which is a 40% reduction in silicon area to the traditional one, that can sustain the HBM (MM) ESD stress of 3.5kV (250V).

AB - A new power-rail ESD clamp circuit is proposed and verified with consideration of the gate leakage issue in 65-nm CMOS technology. The proposed circuit can reduce the total leakage current of the traditional power-rail ESD clamp circuit in two orders of magnitude. Moreover, the proposed circuit reduces the required silicon area by boosting the capacitor with a current mirror. The measured leakage current of the proposed power-rail ESD clamp circuit is 220nA (VDD = 1V, T=25°C), much lower than the 20.55μA of the traditional design. In addition, the required area for the proposed design is 50μm × 30μm, which is a 40% reduction in silicon area to the traditional one, that can sustain the HBM (MM) ESD stress of 3.5kV (250V).

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T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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BT - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013

T2 - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013

Y2 - 19 May 2013 through 23 May 2013

ER -

Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology

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