Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

Chang Tzu Wang; Ming-Dou Ker; Tien Hao Tang; Kuan Cheng Su

doi:10.1109/ICICDT.2009.5166256

Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

Chang Tzu Wang^*, Ming-Dou Ker, Tien Hao Tang, Kuan Cheng Su

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7kV human-body-model (HBM) and 325V machine model (MM) ESD tests which occupying an silicon area of only 49μmx21μm and consuming a very low standby leakage current of 96nA at room temperature.

Original language	English
Title of host publication	2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
Pages	21-24
Number of pages	4
DOIs	https://doi.org/10.1109/ICICDT.2009.5166256
State	Published - 1 Dec 2009
Event	2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 - Austin, TX, United States Duration: 18 May 2009 → 20 May 2009

Publication series

Name	2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

Conference

Conference	2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
Country/Territory	United States
City	Austin, TX
Period	18/05/09 → 20/05/09

Keywords

Electrostatic discharge (ESD)
Gate leakage
Power-rail ESD clamp circuit
Silicon controlled rectifier (SCR)

Access to Document

10.1109/ICICDT.2009.5166256

Cite this

Wang, C. T., Ker, M.-D., Tang, T. H., & Su, K. C. (2009). Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology. In 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 (pp. 21-24). Article 5166256 (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009). https://doi.org/10.1109/ICICDT.2009.5166256

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title = "Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology",

abstract = "A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7kV human-body-model (HBM) and 325V machine model (MM) ESD tests which occupying an silicon area of only 49μmx21μm and consuming a very low standby leakage current of 96nA at room temperature.",

keywords = "Electrostatic discharge (ESD), Gate leakage, Power-rail ESD clamp circuit, Silicon controlled rectifier (SCR)",

author = "Wang, {Chang Tzu} and Ming-Dou Ker and Tang, {Tien Hao} and Su, {Kuan Cheng}",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/ICICDT.2009.5166256",

language = "English",

isbn = "9781424429332",

series = "2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009",

pages = "21--24",

booktitle = "2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009",

note = "2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 ; Conference date: 18-05-2009 Through 20-05-2009",

}

Wang, CT, Ker, M-D, Tang, TH & Su, KC 2009, Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology. in 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009., 5166256, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009, pp. 21-24, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009, Austin, TX, United States, 18/05/09. https://doi.org/10.1109/ICICDT.2009.5166256

Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology. / Wang, Chang Tzu; Ker, Ming-Dou; Tang, Tien Hao et al.
2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. 2009. p. 21-24 5166256 (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Wang, Chang Tzu

AU - Ker, Ming-Dou

AU - Tang, Tien Hao

AU - Su, Kuan Cheng

PY - 2009/12/1

Y1 - 2009/12/1

N2 - A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7kV human-body-model (HBM) and 325V machine model (MM) ESD tests which occupying an silicon area of only 49μmx21μm and consuming a very low standby leakage current of 96nA at room temperature.

AB - A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7kV human-body-model (HBM) and 325V machine model (MM) ESD tests which occupying an silicon area of only 49μmx21μm and consuming a very low standby leakage current of 96nA at room temperature.

KW - Electrostatic discharge (ESD)

KW - Gate leakage

KW - Power-rail ESD clamp circuit

KW - Silicon controlled rectifier (SCR)

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SN - 9781424429332

T3 - 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

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BT - 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

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Wang CT, Ker MD, Tang TH, Su KC. Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology. In 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. 2009. p. 21-24. 5166256. (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009). doi: 10.1109/ICICDT.2009.5166256

Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

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