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Low-Error Reduced-Width Booth Multipliers for DSP Applications
Shyh-Jye Jou
*
, Meng Hung Tsai
, Ya Lan Tsao
*
Corresponding author for this work
Institute of Electronics
Research output
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Contribution to journal
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Article
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peer-review
62
Scopus citations
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Keyphrases
Low Error
100%
Booth multiplier
100%
DSP Applications
100%
Reduced Height
100%
Critical Path Delay
40%
Compensation Vector
40%
Proposed Architecture
20%
System Application
20%
Transceiver
20%
Gate Count
20%
Filtering System
20%
Truncation
20%
Hardware Reduction
20%
Verilog Code
20%
Pulse Shaping Filter
20%
Compensation Amount
20%
C Code
20%
Engineering
Critical Path
100%
Input Data
100%
Transceiver
50%
Truncation
50%
Design Result
50%
Pulse Shaping
50%
Filter System
50%
Shaping Filter
50%