Low-Error Reduced-Width Booth Multipliers for DSP Applications

Shyh-Jye Jou*, Meng Hung Tsai, Ya Lan Tsao

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

57 Scopus citations

Abstract

A low-error reduced-width Booth multiplier using a proper compensation vector is proposed. The compensation vector is dependent on the input data. The compensation value will thus be adaptively adjusted when the input data are different. Design results from a 16 × 16 to 16 Booth multiplier show that the gate counts and critical path delay of the new reduced-width multipliers is 50.94% and 66.04% of the post-truncation reduced-width multiplier. A module generator of our proposed architecture is developed that will generate C code and Verilog code for each reduced-width multiplier. Pulse-shaping filter-system applications used in CATV transceivers show promising performance with 50.04% hardware reduction and 33.82% reduction in the critical path delay.

Original languageEnglish
Pages (from-to)1470-1474
Number of pages5
JournalIEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
Volume50
Issue number11
DOIs
StatePublished - 1 Nov 2003

Keywords

  • Compensation vector
  • Digital signal-processing (DSP) application
  • Reduced-width Booth multiplier

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