Low computation cycle and high speed recursive DFT/IDFT: VLSI algorithm and architecture

Lan-Da Van; Yuan Chu Yu; Chun Ming Huang; Chin Teng Lin

doi:10.1109/SIPS.2005.1579933

Low computation cycle and high speed recursive DFT/IDFT: VLSI algorithm and architecture

Lan-Da Van^*, Yuan Chu Yu, Chun Ming Huang, Chin Teng Lin

^*Corresponding author for this work

Institute of Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Scopus citations

Abstract

In this paper, we propose two low-computation cycle and high-speed recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architectures adopting the hybrid of Chebyshev polynomial and register-splitting scheme. The proposed core-type recursive architecture achieves half computation-cycle reduction as well as less critical period compared with the conventional second-order DFT/IDFT architecture. So as to further reduce the number of computation cycles, based on the new core-type design, we develop the folded-type recursive DFT/IDFT architecture with the same operating frequency. Moreover, from the derivation results, the operation of DFT and IDFT can be performed with the same structure under different configurations.

Original language	English
Title of host publication	SiPS 2005
Subtitle of host publication	IEEE Workshop on Signal Processing Systems - Design and Implementation, Proceedings
Pages	579-584
Number of pages	6
DOIs	https://doi.org/10.1109/SIPS.2005.1579933
State	Published - 1 Dec 2005
Event	SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation - Athens, Greece Duration: 2 Nov 2005 → 4 Nov 2005

Publication series

Name	IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Volume	2005
ISSN (Print)	1520-6130

Conference

Conference	SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation
Country/Territory	Greece
City	Athens
Period	2/11/05 → 4/11/05

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10.1109/SIPS.2005.1579933

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Van, L-D., Yu, Y. C., Huang, C. M., & Lin, C. T. (2005). Low computation cycle and high speed recursive DFT/IDFT: VLSI algorithm and architecture. In SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation, Proceedings (pp. 579-584). Article 1579933 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation; Vol. 2005). https://doi.org/10.1109/SIPS.2005.1579933

@inproceedings{4ae74675ed1344c18a3c13ab14d1ad17,

title = "Low computation cycle and high speed recursive DFT/IDFT: VLSI algorithm and architecture",

abstract = "In this paper, we propose two low-computation cycle and high-speed recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architectures adopting the hybrid of Chebyshev polynomial and register-splitting scheme. The proposed core-type recursive architecture achieves half computation-cycle reduction as well as less critical period compared with the conventional second-order DFT/IDFT architecture. So as to further reduce the number of computation cycles, based on the new core-type design, we develop the folded-type recursive DFT/IDFT architecture with the same operating frequency. Moreover, from the derivation results, the operation of DFT and IDFT can be performed with the same structure under different configurations.",

author = "Lan-Da Van and Yu, {Yuan Chu} and Huang, {Chun Ming} and Lin, {Chin Teng}",

year = "2005",

month = dec,

day = "1",

doi = "10.1109/SIPS.2005.1579933",

language = "English",

isbn = "0780393341",

series = "IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation",

pages = "579--584",

booktitle = "SiPS 2005",

note = "SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation ; Conference date: 02-11-2005 Through 04-11-2005",

}

Van, L-D, Yu, YC, Huang, CM & Lin, CT 2005, Low computation cycle and high speed recursive DFT/IDFT: VLSI algorithm and architecture. in SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation, Proceedings., 1579933, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, vol. 2005, pp. 579-584, SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation, Athens, Greece, 2/11/05. https://doi.org/10.1109/SIPS.2005.1579933

Low computation cycle and high speed recursive DFT/IDFT: VLSI algorithm and architecture. / Van, Lan-Da; Yu, Yuan Chu; Huang, Chun Ming et al.
SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation, Proceedings. 2005. p. 579-584 1579933 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Yu, Yuan Chu

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AU - Lin, Chin Teng

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N2 - In this paper, we propose two low-computation cycle and high-speed recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architectures adopting the hybrid of Chebyshev polynomial and register-splitting scheme. The proposed core-type recursive architecture achieves half computation-cycle reduction as well as less critical period compared with the conventional second-order DFT/IDFT architecture. So as to further reduce the number of computation cycles, based on the new core-type design, we develop the folded-type recursive DFT/IDFT architecture with the same operating frequency. Moreover, from the derivation results, the operation of DFT and IDFT can be performed with the same structure under different configurations.

AB - In this paper, we propose two low-computation cycle and high-speed recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architectures adopting the hybrid of Chebyshev polynomial and register-splitting scheme. The proposed core-type recursive architecture achieves half computation-cycle reduction as well as less critical period compared with the conventional second-order DFT/IDFT architecture. So as to further reduce the number of computation cycles, based on the new core-type design, we develop the folded-type recursive DFT/IDFT architecture with the same operating frequency. Moreover, from the derivation results, the operation of DFT and IDFT can be performed with the same structure under different configurations.

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ER -

Low computation cycle and high speed recursive DFT/IDFT: VLSI algorithm and architecture

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